- 28 May, 2019 1 commit
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[VTA][TSIM] Use Module instead of RawModule for testbench by creating an empty bundle for the IO (#3242) * use Module instead of RawModule for testbench by creating an empty bundle for the IO * change default back to verilog
Luis Vega committed
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- 20 May, 2019 1 commit
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Luis Vega committed
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- 08 May, 2019 1 commit
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* merge files * move verilator to the right place * change name to tsim * add default rule to be build and run * add README for tsim * Update README.md * add some structural feedback * change name of VTASim to VTADPISim * more renaming * update comment * add license * fix indentation * add switch for vta-tsim * add more licenses * update readme * address some of the new feedback * add some feedback from cpplint * add one more whitespace * pass pointer so linter is happy * pass pointer so linter is happy * README moved to vta documentation * create types for dpi functions, so they can be handle easily * fix pointer style * add feedback from docs * parametrize width data and pointers * fix comments * fix comment * add comment to class * add missing parameters * move README back to tsim example * add feedback * add more comments and remove un-necessary argument in finish * update comments * fix cpplint * fix doc
Luis Vega committed
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- 12 Jul, 2018 10 commits
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tqchen committed
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Thierry Moreau committed
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Yaman Umuroglu committed
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* bug fix for new drivers in new PYNQ image v2.1 * updating instructions for resnet inference * updated the instructions for starting the RPC server * deriving host/port from env for unit tests
Thierry Moreau committed -
Thierry Moreau committed
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Thierry Moreau committed
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Tianqi Chen committed
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tqchen committed
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* VTA python library * Python unit tests * End to end example with Resnet18 * README instructions * Bug fixes
Thierry Moreau committed -
Thierry Moreau committed
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