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Commit 1b359035 by Luis Vega Committed by Tianqi Chen
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[VTA] [TSIM] Improve tsim example (#3206)

parent b7e6976b
Showing with 71 additions and 98 deletions
vta/apps/tsim_example/CMakeLists.txt
......@@ -35,5 +35,5 @@ if (CMAKE_CXX_COMPILER_ID MATCHES "GNU" AND
endif()
# Module rules
include(cmake/modules/tsim.cmake)
include(cmake/modules/driver.cmake)
include(cmake/modules/hw.cmake)
include(cmake/modules/sw.cmake)
vta/apps/tsim_example/Makefile
......@@ -17,16 +17,7 @@
export PYTHONPATH:=$(PWD)/python:$(PYTHONPATH)
BUILD_DIR = $(shell python python/tsim/config.py --get-build-name)
TVM_DIR = $(abspath ../../../)
TSIM_TARGET = verilog
TSIM_TOP_NAME = TestAccel
TSIM_BUILD_NAME = build
# optional
TSIM_TRACE_NAME = trace.vcd
BUILD_DIR = $(shell python3 config/config.py --get-build-name)
default: cmake run
......@@ -39,7 +30,7 @@ $(BUILD_DIR):
mkdir -p $@
run:
python3 tests/python/test_tsim.py | grep PASS
python3 tests/python/add_by_one.py | grep PASS
clean:
-rm -rf $(BUILD_DIR)
vta/apps/tsim_example/README.md
......@@ -64,8 +64,8 @@ These examples are located at `<tvm-root>/vta/apps/tsim_example`.
* Run `make`
* Some pointers
* Build cmake script for driver `<tvm-root>/vta/apps/tsim_example/cmake/modules/driver.cmake`
* Build cmake script for tsim `<tvm-root>/vta/apps/tsim_example/cmake/modules/tsim.cmake`
* Software driver that handles the VTA accelerator `<tvm-root>/vta/apps/tsim_example/src/driver.cc`
* VTA add-by-one accelerator (Verilog) `<tvm-root>/vta/apps/tsim_example/hardware/verilog`
* VTA add-by-one accelerator (Chisel) `<tvm-root>/vta/apps/tsim_example/hardware/chisel`
* Build cmake script for software library`<tvm-root>/vta/apps/tsim_example/cmake/modules/sw.cmake`
* Build cmake script for hardware library`<tvm-root>/vta/apps/tsim_example/cmake/modules/hw.cmake`
* Software driver that handles the accelerator `<tvm-root>/vta/apps/tsim_example/src/driver.cc`
* Add-by-one accelerator in Verilog `<tvm-root>/vta/apps/tsim_example/hardware/verilog`
* Add-by-one accelerator in Chisel3 `<tvm-root>/vta/apps/tsim_example/hardware/chisel`
vta/apps/tsim_example/cmake/modules/tsim.cmake → vta/apps/tsim_example/cmake/modules/hw.cmake
......@@ -16,7 +16,7 @@
# under the License.
if(MSVC)
message(STATUS "TSIM build is skipped in Windows..")
message(STATUS "[TSIM_HW] build is skipped in Windows..")
else()
find_program(PYTHON NAMES python python3 python3.6)
find_program(VERILATOR NAMES verilator)
......@@ -24,26 +24,20 @@ else()
if (VERILATOR AND PYTHON)
if (TSIM_TOP_NAME STREQUAL "")
message(FATAL_ERROR "TSIM_TOP_NAME should be defined")
message(FATAL_ERROR "[TSIM_HW] TSIM_TOP_NAME should be defined")
endif()
if (TSIM_BUILD_NAME STREQUAL "")
message(FATAL_ERROR "TSIM_BUILD_NAME should be defined")
message(FATAL_ERROR "[TSIM_HW] TSIM_BUILD_NAME should be defined")
endif()
set(TSIM_CONFIG ${PYTHON} ${CMAKE_CURRENT_SOURCE_DIR}/python/tsim/config.py)
set(TSIM_CONFIG ${PYTHON} ${CMAKE_CURRENT_SOURCE_DIR}/config/config.py)
execute_process(COMMAND ${TSIM_CONFIG} --get-target OUTPUT_VARIABLE __TSIM_TARGET)
execute_process(COMMAND ${TSIM_CONFIG} --get-top-name OUTPUT_VARIABLE __TSIM_TOP_NAME)
execute_process(COMMAND ${TSIM_CONFIG} --get-build-name OUTPUT_VARIABLE __TSIM_BUILD_NAME)
execute_process(COMMAND ${TSIM_CONFIG} --get-use-trace OUTPUT_VARIABLE __TSIM_USE_TRACE)
execute_process(COMMAND ${TSIM_CONFIG} --get-trace-name OUTPUT_VARIABLE __TSIM_TRACE_NAME)
string(STRIP ${__TSIM_TARGET} TSIM_TARGET)
string(STRIP ${__TSIM_TOP_NAME} TSIM_TOP_NAME)
string(STRIP ${__TSIM_BUILD_NAME} TSIM_BUILD_NAME)
string(STRIP ${__TSIM_USE_TRACE} TSIM_USE_TRACE)
string(STRIP ${__TSIM_TRACE_NAME} TSIM_TRACE_NAME)
execute_process(COMMAND ${TSIM_CONFIG} --get-target OUTPUT_VARIABLE TSIM_TARGET OUTPUT_STRIP_TRAILING_WHITESPACE)
execute_process(COMMAND ${TSIM_CONFIG} --get-top-name OUTPUT_VARIABLE TSIM_TOP_NAME OUTPUT_STRIP_TRAILING_WHITESPACE)
execute_process(COMMAND ${TSIM_CONFIG} --get-build-name OUTPUT_VARIABLE TSIM_BUILD_NAME OUTPUT_STRIP_TRAILING_WHITESPACE)
execute_process(COMMAND ${TSIM_CONFIG} --get-use-trace OUTPUT_VARIABLE TSIM_USE_TRACE OUTPUT_STRIP_TRAILING_WHITESPACE)
execute_process(COMMAND ${TSIM_CONFIG} --get-trace-name OUTPUT_VARIABLE TSIM_TRACE_NAME OUTPUT_STRIP_TRAILING_WHITESPACE)
set(TSIM_BUILD_DIR ${CMAKE_CURRENT_SOURCE_DIR}/${TSIM_BUILD_NAME})
......@@ -60,24 +54,24 @@ else()
COMMAND ${SBT} publishLocal RESULT_VARIABLE RETCODE)
if (NOT RETCODE STREQUAL "0")
message(FATAL_ERROR "[TSIM] sbt failed to install VTA scala package")
message(FATAL_ERROR "[TSIM_HW] sbt failed to install VTA scala package")
endif()
# Chisel - Scala to Verilog compilation
set(TSIM_CHISEL_DIR ${CMAKE_CURRENT_SOURCE_DIR}/hardware/chisel)
set(CHISEL_TARGET_DIR ${TSIM_BUILD_DIR}/chisel)
set(CHISEL_OPT "test:runMain test.Elaborate --target-dir ${CHISEL_TARGET_DIR} --top-name ${TSIM_TOP_NAME}")
set(CHISEL_BUILD_DIR ${TSIM_BUILD_DIR}/chisel)
set(CHISEL_OPT "test:runMain test.Elaborate --target-dir ${CHISEL_BUILD_DIR} --top-name ${TSIM_TOP_NAME}")
execute_process(WORKING_DIRECTORY ${TSIM_CHISEL_DIR} COMMAND ${SBT} ${CHISEL_OPT} RESULT_VARIABLE RETCODE)
if (NOT RETCODE STREQUAL "0")
message(FATAL_ERROR "[TSIM] sbt failed to compile from Chisel to Verilog.")
message(FATAL_ERROR "[TSIM_HW] sbt failed to compile from Chisel to Verilog.")
endif()
file(GLOB VERILATOR_RTL_SRC ${CHISEL_TARGET_DIR}/*.v)
file(GLOB VERILATOR_RTL_SRC ${CHISEL_BUILD_DIR}/*.v)
else()
message(FATAL_ERROR "[TSIM] sbt should be installed for Chisel")
message(FATAL_ERROR "[TSIM_HW] sbt should be installed for Chisel")
endif() # sbt
elseif (TSIM_TARGET STREQUAL "verilog")
......@@ -87,24 +81,24 @@ else()
file(GLOB VERILATOR_RTL_SRC ${VTA_VERILOG_DIR}/*.v ${TSIM_VERILOG_DIR}/*.v)
else()
message(STATUS "[TSIM] target language can be only verilog or chisel...")
message(FATAL_ERROR "[TSIM_HW] target language can be only verilog or chisel...")
endif() # TSIM_TARGET
if (TSIM_TARGET STREQUAL "chisel" OR TSIM_TARGET STREQUAL "verilog")
# Check if tracing can be enabled
if (NOT TSIM_USE_TRACE STREQUAL "OFF")
message(STATUS "[TSIM] Verilog enable tracing")
message(STATUS "[TSIM_HW] Verilog enable tracing")
else()
message(STATUS "[TSIM] Verilator disable tracing")
message(STATUS "[TSIM_HW] Verilator disable tracing")
endif()
# Verilator - Verilog to C++ compilation
set(VERILATOR_TARGET_DIR ${TSIM_BUILD_DIR}/verilator)
set(VERILATOR_BUILD_DIR ${TSIM_BUILD_DIR}/verilator)
set(VERILATOR_OPT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_REG_INIT)
list(APPEND VERILATOR_OPT +define+RANDOMIZE_MEM_INIT --x-assign unique)
list(APPEND VERILATOR_OPT --output-split 20000 --output-split-cfuncs 20000)
list(APPEND VERILATOR_OPT --top-module ${TSIM_TOP_NAME} -Mdir ${VERILATOR_TARGET_DIR})
list(APPEND VERILATOR_OPT --top-module ${TSIM_TOP_NAME} -Mdir ${VERILATOR_BUILD_DIR})
list(APPEND VERILATOR_OPT --cc ${VERILATOR_RTL_SRC})
if (NOT TSIM_USE_TRACE STREQUAL "OFF")
......@@ -114,7 +108,7 @@ else()
execute_process(COMMAND ${VERILATOR} ${VERILATOR_OPT} RESULT_VARIABLE RETCODE)
if (NOT RETCODE STREQUAL "0")
message(FATAL_ERROR "[TSIM] Verilator failed to compile Verilog to C++...")
message(FATAL_ERROR "[TSIM_HW] Verilator failed to compile Verilog to C++...")
endif()
# Build shared library (.so)
......@@ -126,9 +120,9 @@ else()
list(APPEND VERILATOR_LIB_SRC ${VERILATOR_INC_DIR}/verilated_vcd_c.cpp)
endif()
file(GLOB VERILATOR_GEN_SRC ${VERILATOR_TARGET_DIR}/*.cpp)
file(GLOB VERILATOR_GEN_SRC ${VERILATOR_BUILD_DIR}/*.cpp)
file(GLOB VERILATOR_SRC ${VTA_HW_DPI_DIR}/tsim_device.cc)
add_library(tsim SHARED ${VERILATOR_LIB_SRC} ${VERILATOR_GEN_SRC} ${VERILATOR_SRC})
add_library(hw SHARED ${VERILATOR_LIB_SRC} ${VERILATOR_GEN_SRC} ${VERILATOR_SRC})
set(VERILATOR_DEF VL_TSIM_NAME=V${TSIM_TOP_NAME} VL_PRINTF=printf VM_COVERAGE=0 VM_SC=0)
if (NOT TSIM_USE_TRACE STREQUAL "OFF")
......@@ -136,17 +130,17 @@ else()
else()
list(APPEND VERILATOR_DEF VM_TRACE=0)
endif()
target_compile_definitions(tsim PRIVATE ${VERILATOR_DEF})
target_compile_options(tsim PRIVATE -Wno-sign-compare -include V${TSIM_TOP_NAME}.h)
target_include_directories(tsim PRIVATE ${VERILATOR_TARGET_DIR} ${VERILATOR_INC_DIR} ${VERILATOR_INC_DIR}/vltstd ${VTA_DIR}/include)
target_compile_definitions(hw PRIVATE ${VERILATOR_DEF})
target_compile_options(hw PRIVATE -Wno-sign-compare -include V${TSIM_TOP_NAME}.h)
target_include_directories(hw PRIVATE ${VERILATOR_BUILD_DIR} ${VERILATOR_INC_DIR} ${VERILATOR_INC_DIR}/vltstd ${VTA_DIR}/include)
if(APPLE)
set_target_properties(tsim PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
set_target_properties(hw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
endif(APPLE)
endif() # TSIM_TARGET STREQUAL "chisel" OR TSIM_TARGET STREQUAL "verilog"
else()
message(STATUS "[TSIM] could not find Python or Verilator, build is skipped...")
message(STATUS "[TSIM_HW] could not find Python or Verilator, build is skipped...")
endif() # VERILATOR
endif() # MSVC
vta/apps/tsim_example/cmake/modules/driver.cmake → vta/apps/tsim_example/cmake/modules/sw.cmake
......@@ -16,9 +16,9 @@
# under the License.
file(GLOB TSIM_SW_SRC src/driver.cc)
add_library(driver SHARED ${TSIM_SW_SRC})
target_include_directories(driver PRIVATE ${VTA_DIR}/include)
add_library(sw SHARED ${TSIM_SW_SRC})
target_include_directories(sw PRIVATE ${VTA_DIR}/include)
if(APPLE)
set_target_properties(driver PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
set_target_properties(sw PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
endif(APPLE)
vta/apps/tsim_example/python/tsim/config.json → vta/apps/tsim_example/config/config.json
......@@ -2,6 +2,6 @@
"TARGET" : "verilog",
"TOP_NAME" : "TestAccel",
"BUILD_NAME" : "build",
"USE_TRACE" : "off",
"USE_TRACE" : "OFF",
"TRACE_NAME" : "trace"
}
vta/apps/tsim_example/python/tsim/load.py → vta/apps/tsim_example/python/tsim/driver.py
......@@ -21,36 +21,24 @@ import json
import os.path as osp
from sys import platform
def get_build_path():
curr_path = osp.dirname(osp.abspath(osp.expanduser(__file__)))
cfg = json.load(open(osp.join(curr_path, 'config.json')))
return osp.join(curr_path, "..", "..", cfg['BUILD_NAME'])
def get_lib_ext():
if platform == "darwin":
ext = ".dylib"
else:
ext = ".so"
return ext
def get_lib_path(name):
build_path = get_build_path()
ext = get_lib_ext()
libname = name + ext
return osp.join(build_path, libname)
def _load_driver_lib():
lib = get_lib_path("libdriver")
try:
return [ctypes.CDLL(lib, ctypes.RTLD_GLOBAL)]
except OSError:
return []
def load_driver():
return tvm.get_global_func("tvm.vta.driver")
def load_tsim():
lib = get_lib_path("libtsim")
return tvm.module.load(lib, "vta-tsim")
LIBS = _load_driver_lib()
def driver(hw, sw):
_cur_path = osp.dirname(osp.abspath(osp.expanduser(__file__)))
_root_path = osp.join(_cur_path, "..", "..")
_cfg_file = osp.join(_root_path, "config", "config.json")
_cfg = json.load(open(_cfg_file))
_ext = ".dylib" if platform == "darwin" else ".so"
_hw_lib = osp.join(_root_path, _cfg['BUILD_NAME'], hw + _ext)
_sw_lib = osp.join(_root_path, _cfg['BUILD_NAME'], sw + _ext)
def load_dll(dll):
try:
return [ctypes.CDLL(dll, ctypes.RTLD_GLOBAL)]
except OSError:
return []
def run(a, b):
load_dll(_sw_lib)
f = tvm.get_global_func("tvm.vta.driver")
m = tvm.module.load(_hw_lib, "vta-tsim")
f(m, a, b)
return run
vta/apps/tsim_example/src/driver.cc
......@@ -35,9 +35,9 @@ uint32_t get_half_addr(void *p, bool upper) {
using vta::dpi::DPIModuleNode;
using tvm::runtime::Module;
class TestDriver {
class Device {
public:
TestDriver(Module module)
Device(Module module)
: module_(module) {
dpi_ = static_cast<DPIModuleNode*>(
module.operator->());
......@@ -71,7 +71,6 @@ class TestDriver {
}
}
private:
DPIModuleNode* dpi_;
Module module_;
};
......@@ -84,7 +83,7 @@ TVM_REGISTER_GLOBAL("tvm.vta.driver")
Module dev_mod = args[0];
DLTensor* A = args[1];
DLTensor* B = args[2];
TestDriver dev_(dev_mod);
Device dev_(dev_mod);
dev_.Run(A->shape[0], A->data, B->data);
});
......
vta/apps/tsim_example/tests/python/test_tsim.py → vta/apps/tsim_example/tests/python/add_by_one.py
......@@ -17,7 +17,8 @@
import tvm
import numpy as np
from tsim.load import load_driver, load_tsim
from tsim.driver import driver
def test_tsim(i):
rmin = 1 # min vector size of 1
......@@ -26,13 +27,13 @@ def test_tsim(i):
ctx = tvm.cpu(0)
a = tvm.nd.array(np.random.randint(rmax, size=n).astype("uint64"), ctx)
b = tvm.nd.array(np.zeros(n).astype("uint64"), ctx)
tsim = load_tsim()
f = load_driver()
f(tsim, a, b)
f = driver("libhw", "libsw")
f(a, b)
emsg = "[FAIL] test number:{} n:{}".format(i, n)
np.testing.assert_equal(b.asnumpy(), a.asnumpy() + 1, err_msg=emsg)
print("[PASS] test number:{} n:{}".format(i, n))
if __name__ == "__main__":
for i in range(10):
times = 10
for i in range(times):
test_tsim(i)
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