- 28 Jun, 2019 8 commits
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* init init lint rename ci fix add add some doc save add some test add some test lint lint lint * fix build
雾雨魔理沙 committed -
* save * fix
雾雨魔理沙 committed -
* Nested rfactor fix, update predicates as well as source. * Linter * Syntax fix.
Christian Sarofeen committed -
* Add sequence_mask use exactly the same arguments as mxnet fix * fix lint * fix lint * add mxnet conversion + relay * update * update doc * fix pylint * fix doc * address comment * try to address comments * try to enable shape check for valid_length * fix * try to fix * fix bug * try to fix * address comment * address comment
Xingjian Shi committed -
Amy Wang committed
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雾雨魔理沙 committed
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hlu1 committed
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* simplify build script, remove python 2 support * remove py2 file * update py3
雾雨魔理沙 committed
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- 27 Jun, 2019 9 commits
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* fix relay reduce axis bug * add tests for reduce bug
Altan Haan committed -
ttyang1018 committed
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Yao Wang committed
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Discovered via: __flake8 . --count --select=E9,F63,F72,F82 --show-source --statistics__ Legacy __print__ statements are syntax errors in Python 3 but __print()__ function works as expected in both Python 2 and Python 3.
cclauss committed -
[Symptom] after follow the tsim example readme, doing verilator install by 'sudo apt-get-install verilator' Once enable 'debug' or manually add 'printf' logic in chisel module, verilator would report following error. 'syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER' [Fix] upgrade verilator to 4.012, issue fixed. [Solution] Link README.md verilator install steps with verilator home website install instruction.
Hua Jiang committed -
Alexander Pivovarov committed
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Discovered via: __flake8 . --count --select=E9,F63,F72,F82 --show-source --statistics__
cclauss committed -
Li committed
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* [AutoTVM] Fix a bug in simulated annealing * Update sa_model_optimizer.py
Lianmin Zheng committed
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- 25 Jun, 2019 4 commits
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Yong Wu committed
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* [VTA] Add VTA PYNQ metal_test bitstream program logic and fix couple compile issue. Issue: VTAProgram not exist and cause compile error. No logic to program the bitstream into FPGA. metal test still use pynq 2.1 library which not support on latest pynq 2.4. Solution: remove old VTAProgram. when setting is pynq, program the bitstream during compile. change DMA link library to libcma. * Address review commends.
Hua Jiang committed -
Summary: In multi-threaded applications where we have multiple inferences on the same model in parallel (consider e.g. a TTS system handling multiple requests), it can be useful to share the parameters of a model amongst these multiple instances. This improves the cache utilization behaviour of the system, as multiple cores can use the same set of weights instead of evicting the identical copies of weights in a shared cache. As the underlying `NDArray` instances in `data_entry_` implement a ref-counted based sharing system, this is a simple modification of the `GraphRuntime::LoadParams` logic to instead copy parameters from an existing GraphRuntime instance. This is a little ugly in that we need both the pre-existing GraphRuntime instance, as well as the 'serialized' params (since we need to know the set of names we should copy), but without imposing additional assumptions (i.e. storing the set of param names in GraphRuntime, and enforcing that shared param names are identical to the parameters set in the preceding `LoadParams` call), this seems unavoidable. Test Plan: Unit test added.
Andrew Tulloch committed -
Sammy committed
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- 24 Jun, 2019 2 commits
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雾雨魔理沙 committed
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Alexander Pivovarov committed
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- 23 Jun, 2019 1 commit
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* Support bidirectional RNN layer * tweak * tweak
Haichen Shen committed
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- 22 Jun, 2019 5 commits
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雾雨魔理沙 committed
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* [QUANTIZE] Support for clip operator * [QUANTIZE] Memorizing the quantize node mapping. * [QUANTIZE] Remove use_stop_fusion and skip_k_conv in qconfig * update * update * update * update
ziheng committed -
Wei Chen committed
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Wei Chen committed
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Jessica Davies committed
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- 21 Jun, 2019 2 commits
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* update README * fix typo
Luis Vega committed -
Lianmin Zheng committed
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- 20 Jun, 2019 5 commits
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* Add EtaExpand to transform API * Add test case
Wei Chen committed -
henrywu2019 committed
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Wuwei Lin committed
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Zhi committed
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Issue: when using vivado compile vta.cc with top function 'vta', vivado report deadlock error like '...with default size is used in a non -dataflow region, which may result in deadlock Please consider to resize the stream using the directive ‘set_directive_stream’ or the ‘HL S stream’ pragma.' Solution: give the queue a default size as 8.
Hua Jiang committed
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- 19 Jun, 2019 2 commits
- 18 Jun, 2019 2 commits
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* [CI] Update ci-gpu to v0.52 * update nodejs
Tianqi Chen committed -
Alexander Pivovarov committed
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