1. 09 Mar, 2020 1 commit
    • [VTA][Chisel,de10nano] Chisel fixes and de10nano support (#4986) · 5b4cf5df
      * [VTA][de10nano] Enable user defined target frequency.
      
      Issue:
      The VTA target frequency on the DE10-Nano is hardcoded to 50MHz
      unnecessarily limiting performance.
      
      Solution:
      Add a PLL to the FPGA sub-system along with support for the
      selection of a user specified frequency at build time. The board
      successfully builds and runs at 100MHz.
      
      * Added a PLL in the soc_system.tcl platform designer generator
        script.
      
      * Modified the Makefile to automatically set the target frequency
        from that specified in the pkg_config.py file.
      
      * Modified the Makefile to generate a bitstream with an RBF
        format that enables programming of the FPGA directly from
        the on-board processor. Specifically, the RBF is generated in
        FastParallel32 mode with compression, which corresponds to the
        default MSEL switch setting on the board, i.e. 01010.
      
      * Added a false path override to file set_clocks.sdc to turn off
        unconstrained path warnings on the VTA pulse LED.
      
      * [VTA][TSIM] Add more debug and tracing options.
      
      * Modified Makefile to change default config to DafaultDe10Config.
      
      * Added option in Makefile to produce more detailed tracing
        for extra observability in debugging complex scenarios.
      
      * Added option in Makefile to produce traces in FST format which
        are 2 orders of magnitude smaller, although much slower to
        generate.
      
      * Added option in Makefile to build the simulator with GCC address
        sanitizer.
      
      * Modified Makefile to not lint the scala code by default avoiding
        unintended wrong indentation. Linting should be better performed
        manually on a per-need basis.
      
      * [VTA][de10nano] Enable remote programming of FPGA.
      
      Issue:
      The Cyclone V FPGA on board of the DE10-Nano can only be programmed
      using the JTAG port, which is a limiting option for users.
      
      Solution:
      Add support for the remote programming of the FPGA implementing
      the FPGA programming manager protocol published in the Cyclone V
      user manual.
      
      * Added file de10nano_mgr.h implementing an FPGA manager class
        that supports handling of control and status registers as well
        as a push-button option to program the FPGA. The class can be
        easily extended to include more registers if needed.
      
      * Used an instance of the FPGA manager to implement function
        VTAProgram also warning users when incompatible bitstream
        files are used.
      
      * Registered VTAProgram as a global function and modified
        the program_bitstream python class to use it.
      
      * [VTA][de10nano] Enhance de10nano runtime support.
      
      Issue:
      The de10nano target has incomplete, non-working support
      for runtime reconfiguration, bitstream programming, and
      examples of usage.
      
      Solution:
      Complete runtime support for the de10nano target.
      
      * Modified VTA.cmake to comment out a default override for
        VTA_MAX_XFER to 21 bit wide.
      
      * Modified VTA.cmake to add needed de10nano include dirs.
      
      * Modified relevant files to support de10nano same way as
        other targets for VTA runtime reconfiguration and FPGA
        programming.
      
      * Added test_program_rpc.py example as a runtime FPGA
        programming example. Note that unlike the pynq target
        no bitstream is either downloaded or programmed when
        the bitstream argument is set to None.
      
      * Cosmetic changes to vta config files.
      
      * [VTA][Chisel] LoadUop FSM bug fix.
      
      Issue:
      The LoadUop FSM incorrectly advances the address of the next
      uop to read from DRAM when the DRAM data valid bit is deasserted
      and asserted at the end of a read. This is caused by a mismatch
      in the logic of the state and output portions of the FSM.
      This is one of two issues that was gating the correct operation
      of VTA on the DE10-Nano target.
      
      Solution:
      Modify the logic of the output section of the FSM to include
      a check on the DRAM read valid bit or fold the output assignemnt
      into the state section.
      
      * Folded the assignemnt of the next uop address in the state
        section of the FSM.
      
      * [VTA][Chisel] Dynamically adjust DMA tranfer size.
      
      Issue:
      In the DE10-Nano target and possibly in others, DMA transfers that
      cross the boundaries of memory pages result in incorrect reads and
      writes from and to DRAM. When this happens depending on different
      input values, VTA loads and stores exhibit incorrect results for
      DMA pulses at the end of a transfer. This is one of two issues that
      were gating the DE10-Nano target from functioning correctly, but may
      affect other Chisel based targets.
      
      Solution:
      Add support for dynamically adjustble DMA transfer sizes in load
      and store operations. For a more elegant and modular implementation
      the feature can be enabled at compile time with a static constant
      that can be passed as a configuration option.
      
      * Modified the load and store finite state machines to dynamically
        adjust the size of initial and stride DMA transfers. The feature
        is enabled by default by virtue of the static constant
        ADAPTIVE_DMA_XFER_ENABLE.
      
      * [VTA][Chisel] Improve FSIM/TSIM/FPGA xref debug.
      
      Issue:
      Cross reference between FSIM, TSIM, and Chisel based FPGA traces
      is an invaluable instrument that enables fast analysis on FSIM,
      and analysis/debug on TSIM and FPGA, especially for complex flows
      like conv2d or full inferences. Currently this cannot be done
      easily since a suitable reference is missing. The clock cycle
      event counter cannot be used since it is undefined in FSIM and
      not reliable between TSIM and FPGA because of different latencies.
      
      Solution:
      Introduce a new event counter that preserves a program order across
      FSIM, TSIM, FPGA. We propose adding the accumulator write event
      counter in the Chisel EventCounter class and a simple instrumentation
      in the FSIM runtime code. Note that this technique enabled finding the
      Chisel issues reportes in the PR, which would have been otherwise
      far more difficult.
      
      * Added the acc_wr_count event counter and changed interfaces
        accordingly.
      
      * [VTA][de10nano] Comply with linting rules.
      
      * [VTA] Appease make lint.
      
      * [VTA] Disable pylint import not top level error.
      
      * [VTA][Chisel,de10nano] Linting changes.
      
      * Use CamelCase class names.
      
      * Use C++ style C include header files.
      
      * Add comments to Chisel makefile.
      
      * [VTA][de10nano]
      
      * Reorder C and C++ includes in de10nano_mgr.h.
      
      * Restore lint as default target in Chisel Makefile.
      
      * [VTA][de10nano] Do not use f string in pkg_config.py.
      
      * [VTA][de10nano] Remove overlooked f strings in pkg_config.py.
      
      * [VTA][de10nano] Fixed typo.
      
      * [VTA][TSIM] Check if gcc has align-new.
      
      * [VTA][Chisel] Make adaptive DMA transfer default.
      
      * [VTA][RPC] Renamed VTA_PYNQ_RPC_* to VTA_RPC_*.
      
      Issue:
      With more FPGA targets coming online the initial method of
      using individual environment variables to specify target IP and port
      does not scale well.
      
      Solution:
      Use a single VTA_RPC_HOST, VTA_RPC_PORT pair to be changed
      every time a different target is used. For instance in a script
      used to benchmark all targets.
      
      * Replaced every instance of VTA_PYNQ_RPC_HOST and VTA_PYNQ_RPC_PORT
        with VTA_RPC_HOST and VTA_RPC_PORT, respectively.
      
      * [VTA][Chisel] Comply with new linter.
      Pasquale Cocchini committed
  2. 20 Feb, 2020 1 commit
  3. 17 Feb, 2020 1 commit
  4. 26 Nov, 2019 1 commit
  5. 22 Nov, 2019 1 commit
  6. 06 Nov, 2019 1 commit
  7. 21 Oct, 2019 1 commit
  8. 27 Sep, 2019 1 commit
  9. 25 Sep, 2019 1 commit
  10. 13 Sep, 2019 1 commit
  11. 05 Sep, 2019 1 commit
  12. 13 Aug, 2019 1 commit
    • [VTA][TSIM][Build] Towards TSIM CI testing (#3704) · e518fe1c
      * building TSIM specific library along with fast simulator to quickly switch between dlls
      
      * cmake controlled TSIM libraries
      
      * always build tsim driver in either simulation modes
      
      * build DLLs based on CMAKE flags
      
      * updating the jenkinsfile
      
      * small restructuring
      
      * reducing the cmake flags
      
      * update instructions
      
      * reverting to 3 flags
      
      * update Jenkinsfile
      
      * adding new line
      
      * enabling TSIM unit and integration tests
      
      * fix description
      
      * temporarily disabling task_python_vta tests in CPU Build stage
      
      * move CPU tests in unit test stage
      
      * stage  reorg
      
      * better make
      
      * disabling TSIM tests for now
      
      * reverting some restructuring
      
      * fix
      Thierry Moreau committed
  13. 31 Jul, 2019 1 commit
    • [VTA] VTA Compilation Script for Intel FPGA (#3494) · 83591aa5
      * initial compilation script for chisel-vta;
      
      * replace tabs with spaces;
      
      * compile script for de10-nano;
      
      * remove generated verilog source code;
      
      * remove `altsource_probe`, `debounce`, `edge_detect` ip;
      
      * replace quartus project files with a single tcl script;
      
      * Update install.md
      
      * improved makefile-based compilation script;
      
      * complete makefile-based compilation of chisel-vta for de10-nano;
      
      * install quartus;
      
      * conversion to .rbf file;
      
      * document chisel-vta compilation process for de10-nano;
      
      * rename generated bitstream file;
      
      * download and extract custom ip for de10-nano;
      
      * minor change
      
      * minor change
      
      * fix indentation;
      
      * bug fix;
      
      * improved robustness in makefile;
      
      * clean up;
      
      * add `.sdc .ipx .qsys` allowance in jenkins;
      
      * add ASF header;
      
      * add ASF header;
      
      * remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys;
      
      * add ASF header;
      
      * keep sources compact;
      
      * keep sources compact;
      
      * it's not necessary now
      
      * AXI4LiteClient -> AXI3Client for IntelShell
      
      * remove connection to fpga_only_master;
      
      * a few important bug fix: wire reset pin, and set host_r_last to high
      
      * remove intel specific interface definition;
      
      * add NO_DSP option in Makefile;
      
      * AXI4Lite is not used in IntelShell;
      
      * minor fix: disable dsp and use logic instead;
      
      * quartus version change: 18.0 -> 18.1
      
      * remove altera related statement;
      
      * compose compile_design.tcl
      
      * initial tcl script for soc_system generation;
      
      * remove .qsys file;
      
      * remove unused;
      
      * .qsys can be generated by tcl script;
      
      * remove hps_io and shrink size of soc_system;
      
      * integrate into makefile;
      
      * version change: 18.0 -> 18.1
      
      * add sample config file for de10-nano;
      
      * parameterize DEVICE and PROJECT_NAME
      
      * remove extra lines;
      
      * brief description on flashing sd card image for de10-nano
      
      * docs on building additional components
      
      * parameterize DEVICE and DEVICE_FAMILY
      
      * parameterize DEVICE and DEVICE_FAMILY
      
      * parameterize DEVICE and DEVICE_FAMILY
      
      * de10-nano -> de10nano
      
      * minor change
      
      * add comment in code and document in order to address review comments;
      Liangfu Chen committed
  14. 29 Jul, 2019 1 commit
    • [VTA] Refactor to increase platform coverage (Ultra96 etc.) (#3496) · f55609b4
      * hardware refactor for increased FPGA coverage, small optimizations
      
      * fix header
      
      * cleaning up parameters that won't be needed for now
      
      * streamlining makefile, and simplifying tcl scripts
      
      * moving parameter derivation into pkg_config.py, keeping tcl scripts lightweight
      
      * refactoring tcl script to avoid global variables
      
      * deriving AXI signals in pkg_config.py
      
      * unifying address map definition for hardware and software drivers
      
      * single channel design for ultra96 to simplify build
      
      * enable alu by default, no mul opcode for now
      
      * hardware fix
      
      * new bitstream; vta version
      
      * avoid error when env variable is not set
      
      * ultra96 cleanup
      
      * further cleaning up tcl script for bitstream generation
      
      * preliminary rpc server support on ultra96
      
      * rpc server tracker scripts
      
      * ultra96 ldflag
      
      * ultra96 support
      
      * ultra96 support
      
      * cleanup line
      
      * cmake support for ultra96
      
      * simplify memory instantiation
      
      * cleaning up IP parameter initialization
      
      * fix queue instantiation
      
      * 2019.1 transition
      
      * fix macro def
      
      * removing bus width from config
      
      * cleanup
      
      * fix
      
      * turning off testing for now
      
      * cleanup ultra96 ps insantiation
      
      * minor refactor
      
      * adding comments
      
      * upgrading to tophub v0.6
      
      * model used in TVM target now refers to a specific version of VTA for better autoTVM scheduling
      
      * revert change due to bug
      
      * rename driver files to be for zynq-type devices
      
      * streamlining address mapping
      
      * unifying register map offset values between driver and hardware generator
      
      * rely on cma library for cache flush/invalidation
      
      * coherence management
      
      * not make buffer packing depend on data types that can be wider than 64bits
      
      * refactor config derivation to minimize free parameters
      
      * fix environment/pkg config interaction
      
      * adding cfg dump property to pkgconfig:
      
      * fix rpc reconfig
      
      * fix spacing
      
      * cleanup
      
      * fix spacing
      
      * long line fix
      
      * fix spacing and lint
      
      * fix line length
      
      * cmake fix
      
      * environment fix
      
      * renaming after pynq since the driver stack relies on the pynq library - see pynq.io
      
      * update doc
      
      * adding parameterization to  name
      
      * space
      
      * removing reg width
      
      * vta RPC
      
      * update doc on how to edit vta_config.json
      
      * fix path
      
      * fix path
      Thierry Moreau committed
  15. 01 Jun, 2019 1 commit
    • [Bugfix][VTA] PkgConfig cause crash in PYNQ board due to link library (#3257) · f6acf2e5
      * [Bugfix][VTA] PkgConfig cause crash in PYNQ board due to link library
      not exist.
      
      Symptom:
      When run vta_get_started.py with pynq board, host crash and
      complain "cannot find -lsds_lib" and "cannot find -l:libdma.so"
      
      Reproduce:
      At pynq board, delete the ./build/vta_config.json, then run rpc
      server.
      In host machine run vta_get_started.py, issue would reproduce.
      
      Analysis:
      This issue caused by 'PkgConfig' function  still using pynq2.1
      library which not exist in pynq2.4 anymore, when a "reconfig_runtime"
      logic of rpc_server.py get triggered , the compile would failed due to
      link library not exist.
      
      Solution:
      change the link library to libcma.so.
      
      * [Document Change][VTA] Change pynq version from 2.3 into 2.4.
      
      Issue:
      pynq 2.3 image not available anymore from pynq download page and pynq
      2.4 is the current latest image which available in the said website, after
      verification, currently VTA work good with pynq 2.4 image, hence update
      related document from pynq 2.3 to 2.4.
      Hua committed
  16. 16 May, 2019 1 commit
  17. 08 Apr, 2019 1 commit
    • [HEADER] Add Header to Comply with ASF Release Policy (#2982) · cffb4fba
      * [HEADER] ASF header dir=include
      
      * [HEADER] ASF Header dir=src
      
      * [HEADER] ASF Header -dir=python
      
      * [HEADER] ASF header dir=topi
      
      * [HEADER] ASF Header dir=nnvm
      
      * [HEADER] ASF Header -dir=tutorials
      
      * [HEADER] ASF Header dir=tests
      
      * [HEADER] ASF Header -dir=docker
      
      * fix whitespace
      
      * [HEADER] ASF Header -dir=jvm
      
      * [HEADER] ASF Header -dir=web
      
      * [HEADER] ASF Header --dir=apps
      
      * [HEADER] ASF Header --dir=vta
      
      * [HEADER] ASF Header -dir=go
      
      * temp
      
      * [HEADER] ASF Header --dir=rust
      
      * [HEADER] Add ASF Header --dir=cmake
      
      * [HEADER] ASF Header --dir=docs
      
      * [HEADER] Header for Jenkinsfile
      
      * [HEADER] ASF Header to toml and md
      
      * [HEADER] ASF Header to gradle
      
      * Finalize rat cleanup
      
      * Fix permission
      
      * Fix java test
      
      * temporary remove nnvm onnx test
      Tianqi Chen committed
  18. 21 Oct, 2018 1 commit
  19. 03 Aug, 2018 1 commit
  20. 23 Jul, 2018 1 commit
  21. 15 Jul, 2018 1 commit
  22. 13 Jul, 2018 1 commit
  23. 12 Jul, 2018 4 commits