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  1. 05 Aug, 2019 3 commits
  3. 03 Aug, 2019 3 commits
  5. 02 Aug, 2019 6 commits
  7. 01 Aug, 2019 8 commits
  9. 31 Jul, 2019 7 commits
    • [DOC] Update ssd doc to avoid confusion. (#3677) · 3515dccc 
      * intel graphics conv2d bugs fixed for inception_v3

* intel conv2d api updated, nn input size 4 condition added

* review addressed

* move conv_tags to attributes

* ssd doc updated

* address comment
      Leyuan Wang committed
    • [Relay][VM] Relay VM serialization (#3647) · 90455121 
      * relay vm serialization

* fix lint

* load params, fix stream

* lint

* fix typo
      Zhi committed
    • [TEST] Comptiable with python3.5 (#3675) · 0365e50a
      lixiaoquan committed
    • [TOPI][CUDA] schedule for group_conv2d (#3663) · 11da1ca3 
      * [TOPI][CUDA] schedule for group_conv2d

* Fix #flops
      Wuwei Lin committed
    • [VTA] VTA Compilation Script for Intel FPGA (#3494) · 83591aa5 
      * initial compilation script for chisel-vta;

* replace tabs with spaces;

* compile script for de10-nano;

* remove generated verilog source code;

* remove `altsource_probe`, `debounce`, `edge_detect` ip;

* replace quartus project files with a single tcl script;

* Update install.md

* improved makefile-based compilation script;

* complete makefile-based compilation of chisel-vta for de10-nano;

* install quartus;

* conversion to .rbf file;

* document chisel-vta compilation process for de10-nano;

* rename generated bitstream file;

* download and extract custom ip for de10-nano;

* minor change

* minor change

* fix indentation;

* bug fix;

* improved robustness in makefile;

* clean up;

* add `.sdc .ipx .qsys` allowance in jenkins;

* add ASF header;

* add ASF header;

* remove IntelShell.scala, update vta_hw.tcl, clean up Makefile & soc_system.qsys;

* add ASF header;

* keep sources compact;

* keep sources compact;

* it's not necessary now

* AXI4LiteClient -> AXI3Client for IntelShell

* remove connection to fpga_only_master;

* a few important bug fix: wire reset pin, and set host_r_last to high

* remove intel specific interface definition;

* add NO_DSP option in Makefile;

* AXI4Lite is not used in IntelShell;

* minor fix: disable dsp and use logic instead;

* quartus version change: 18.0 -> 18.1

* remove altera related statement;

* compose compile_design.tcl

* initial tcl script for soc_system generation;

* remove .qsys file;

* remove unused;

* .qsys can be generated by tcl script;

* remove hps_io and shrink size of soc_system;

* integrate into makefile;

* version change: 18.0 -> 18.1

* add sample config file for de10-nano;

* parameterize DEVICE and PROJECT_NAME

* remove extra lines;

* brief description on flashing sd card image for de10-nano

* docs on building additional components

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* parameterize DEVICE and DEVICE_FAMILY

* de10-nano -> de10nano

* minor change

* add comment in code and document in order to address review comments;
      Liangfu Chen committed
    • Add yolov3-tiny to the tutorial. (#3674) · 5968eef2
      Balint Cristian committed
    • add reviewer - slyubomirsky (#3673) · f0b4c46f
      Haichen Shen committed
  11. 30 Jul, 2019 10 commits
  13. 29 Jul, 2019 3 commits
    • [VTA] [Chisel] make dram offset configurable for uops different than 4-bytes (#3654) · a88b2842
      Luis Vega committed
    • [VTA] [CMake] hotfix tsim rules (#3650) · 6970fc30
      Luis Vega committed
    • [VTA] Refactor to increase platform coverage (Ultra96 etc.) (#3496) · f55609b4 
      * hardware refactor for increased FPGA coverage, small optimizations

* fix header

* cleaning up parameters that won't be needed for now

* streamlining makefile, and simplifying tcl scripts

* moving parameter derivation into pkg_config.py, keeping tcl scripts lightweight

* refactoring tcl script to avoid global variables

* deriving AXI signals in pkg_config.py

* unifying address map definition for hardware and software drivers

* single channel design for ultra96 to simplify build

* enable alu by default, no mul opcode for now

* hardware fix

* new bitstream; vta version

* avoid error when env variable is not set

* ultra96 cleanup

* further cleaning up tcl script for bitstream generation

* preliminary rpc server support on ultra96

* rpc server tracker scripts

* ultra96 ldflag

* ultra96 support

* ultra96 support

* cleanup line

* cmake support for ultra96

* simplify memory instantiation

* cleaning up IP parameter initialization

* fix queue instantiation

* 2019.1 transition

* fix macro def

* removing bus width from config

* cleanup

* fix

* turning off testing for now

* cleanup ultra96 ps insantiation

* minor refactor

* adding comments

* upgrading to tophub v0.6

* model used in TVM target now refers to a specific version of VTA for better autoTVM scheduling

* revert change due to bug

* rename driver files to be for zynq-type devices

* streamlining address mapping

* unifying register map offset values between driver and hardware generator

* rely on cma library for cache flush/invalidation

* coherence management

* not make buffer packing depend on data types that can be wider than 64bits

* refactor config derivation to minimize free parameters

* fix environment/pkg config interaction

* adding cfg dump property to pkgconfig:

* fix rpc reconfig

* fix spacing

* cleanup

* fix spacing

* long line fix

* fix spacing and lint

* fix line length

* cmake fix

* environment fix

* renaming after pynq since the driver stack relies on the pynq library - see pynq.io

* update doc

* adding parameterization to  name

* space

* removing reg width

* vta RPC

* update doc on how to edit vta_config.json

* fix path

* fix path
      Thierry Moreau committed