Commit 6970fc30 by Luis Vega Committed by Jared Roesch

[VTA] [CMake] hotfix tsim rules (#3650)

parent f55609b4
...@@ -42,18 +42,17 @@ elseif(PYTHON) ...@@ -42,18 +42,17 @@ elseif(PYTHON)
if(${VTA_TARGET} STREQUAL "sim") if(${VTA_TARGET} STREQUAL "sim")
file(GLOB __vta_target_srcs vta/src/sim/*.cc) file(GLOB __vta_target_srcs vta/src/sim/*.cc)
endif() endif()
# Add pynq driver sources
if(${VTA_TARGET} STREQUAL "pynq" OR ${VTA_TARGET} STREQUAL "ultra96")
file(GLOB __vta_target_srcs vta/src/pynq/*.cc)
endif()
list(APPEND VTA_RUNTIME_SRCS ${__vta_target_srcs})
# Add tsim driver sources # Add tsim driver sources
if(${VTA_TARGET} STREQUAL "tsim") if(${VTA_TARGET} STREQUAL "tsim")
target_compile_definitions(vta PUBLIC USE_TSIM) file(GLOB __vta_target_srcs vta/src/tsim/*.cc)
include_directories("vta/include")
file(GLOB RUNTIME_DPI_SRCS vta/src/dpi/module.cc) file(GLOB RUNTIME_DPI_SRCS vta/src/dpi/module.cc)
list(APPEND RUNTIME_SRCS ${RUNTIME_DPI_SRCS}) list(APPEND RUNTIME_SRCS ${RUNTIME_DPI_SRCS})
endif() endif()
# Add pynq driver sources
if(${VTA_TARGET} STREQUAL "pynq" OR ${VTA_TARGET} STREQUAL "ultra96")
file(GLOB __vta_target_srcs vta/src/pynq/*.cc)
endif()
list(APPEND VTA_RUNTIME_SRCS ${__vta_target_srcs})
add_library(vta SHARED ${VTA_RUNTIME_SRCS}) add_library(vta SHARED ${VTA_RUNTIME_SRCS})
...@@ -64,6 +63,12 @@ elseif(PYTHON) ...@@ -64,6 +63,12 @@ elseif(PYTHON)
target_compile_definitions(vta PUBLIC ${__strip_def}) target_compile_definitions(vta PUBLIC ${__strip_def})
endforeach() endforeach()
# Enable tsim macro
if(${VTA_TARGET} STREQUAL "tsim")
include_directories("vta/include")
target_compile_definitions(vta PUBLIC USE_TSIM)
endif()
if(APPLE) if(APPLE)
set_target_properties(vta PROPERTIES LINK_FLAGS "-undefined dynamic_lookup") set_target_properties(vta PROPERTIES LINK_FLAGS "-undefined dynamic_lookup")
endif(APPLE) endif(APPLE)
......
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