Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
T
tic
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
wenyuanbo
tic
Commits
6970fc30
Commit
6970fc30
authored
Jul 29, 2019
by
Luis Vega
Committed by
Jared Roesch
Jul 29, 2019
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
[VTA] [CMake] hotfix tsim rules (#3650)
parent
f55609b4
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
12 additions
and
7 deletions
+12
-7
cmake/modules/VTA.cmake
+12
-7
No files found.
cmake/modules/VTA.cmake
View file @
6970fc30
...
...
@@ -42,18 +42,17 @@ elseif(PYTHON)
if
(
${
VTA_TARGET
}
STREQUAL
"sim"
)
file
(
GLOB __vta_target_srcs vta/src/sim/*.cc
)
endif
()
# Add pynq driver sources
if
(
${
VTA_TARGET
}
STREQUAL
"pynq"
OR
${
VTA_TARGET
}
STREQUAL
"ultra96"
)
file
(
GLOB __vta_target_srcs vta/src/pynq/*.cc
)
endif
()
list
(
APPEND VTA_RUNTIME_SRCS
${
__vta_target_srcs
}
)
# Add tsim driver sources
if
(
${
VTA_TARGET
}
STREQUAL
"tsim"
)
target_compile_definitions
(
vta PUBLIC USE_TSIM
)
include_directories
(
"vta/include"
)
file
(
GLOB __vta_target_srcs vta/src/tsim/*.cc
)
file
(
GLOB RUNTIME_DPI_SRCS vta/src/dpi/module.cc
)
list
(
APPEND RUNTIME_SRCS
${
RUNTIME_DPI_SRCS
}
)
endif
()
# Add pynq driver sources
if
(
${
VTA_TARGET
}
STREQUAL
"pynq"
OR
${
VTA_TARGET
}
STREQUAL
"ultra96"
)
file
(
GLOB __vta_target_srcs vta/src/pynq/*.cc
)
endif
()
list
(
APPEND VTA_RUNTIME_SRCS
${
__vta_target_srcs
}
)
add_library
(
vta SHARED
${
VTA_RUNTIME_SRCS
}
)
...
...
@@ -64,6 +63,12 @@ elseif(PYTHON)
target_compile_definitions
(
vta PUBLIC
${
__strip_def
}
)
endforeach
()
# Enable tsim macro
if
(
${
VTA_TARGET
}
STREQUAL
"tsim"
)
include_directories
(
"vta/include"
)
target_compile_definitions
(
vta PUBLIC USE_TSIM
)
endif
()
if
(
APPLE
)
set_target_properties
(
vta PROPERTIES LINK_FLAGS
"-undefined dynamic_lookup"
)
endif
(
APPLE
)
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment