Commit 5b5ae980 by Luis Vega Committed by Thierry Moreau

add coherent, length, and user bits option to Shell Config (#3593)

parent 3116eeec
...@@ -24,17 +24,18 @@ import chisel3.util._ ...@@ -24,17 +24,18 @@ import chisel3.util._
import vta.util.genericbundle._ import vta.util.genericbundle._
case class AXIParams( case class AXIParams(
coherent: Boolean = false,
addrBits: Int = 32, addrBits: Int = 32,
dataBits: Int = 64 dataBits: Int = 64,
lenBits: Int = 8,
userBits: Int = 1
) )
{ {
require (addrBits > 0) require (addrBits > 0)
require (dataBits >= 8 && dataBits % 2 == 0) require (dataBits >= 8 && dataBits % 2 == 0)
val idBits = 1 val idBits = 1
val userBits = 1
val strbBits = dataBits/8 val strbBits = dataBits/8
val lenBits = 8
val sizeBits = 3 val sizeBits = 3
val burstBits = 2 val burstBits = 2
val lockBits = 2 val lockBits = 2
...@@ -45,11 +46,11 @@ case class AXIParams( ...@@ -45,11 +46,11 @@ case class AXIParams(
val respBits = 2 val respBits = 2
val sizeConst = log2Ceil(dataBits/8) val sizeConst = log2Ceil(dataBits/8)
val idConst = 0 val idConst = 0
val userConst = 0 val userConst = if (coherent) 1 else 0
val burstConst = 1 val burstConst = 1
val lockConst = 0 val lockConst = 0
val cacheConst = 3 val cacheConst = if (coherent) 15 else 3
val protConst = 0 val protConst = if (coherent) 4 else 0
val qosConst = 0 val qosConst = 0
val regionConst = 0 val regionConst = 0
} }
......
...@@ -28,11 +28,17 @@ import vta.interface.axi._ ...@@ -28,11 +28,17 @@ import vta.interface.axi._
class PynqConfig extends Config((site, here, up) => { class PynqConfig extends Config((site, here, up) => {
case ShellKey => ShellParams( case ShellKey => ShellParams(
hostParams = AXIParams( hostParams = AXIParams(
coherent = false,
addrBits = 16, addrBits = 16,
dataBits = 32), dataBits = 32,
lenBits = 8,
userBits = 1),
memParams = AXIParams( memParams = AXIParams(
coherent = true,
addrBits = 32, addrBits = 32,
dataBits = 64), dataBits = 64,
lenBits = 8,
userBits = 1),
vcrParams = VCRParams(), vcrParams = VCRParams(),
vmeParams = VMEParams()) vmeParams = VMEParams())
}) })
...@@ -41,11 +47,17 @@ class PynqConfig extends Config((site, here, up) => { ...@@ -41,11 +47,17 @@ class PynqConfig extends Config((site, here, up) => {
class F1Config extends Config((site, here, up) => { class F1Config extends Config((site, here, up) => {
case ShellKey => ShellParams( case ShellKey => ShellParams(
hostParams = AXIParams( hostParams = AXIParams(
coherent = false,
addrBits = 16, addrBits = 16,
dataBits = 32), dataBits = 32,
lenBits = 8,
userBits = 1),
memParams = AXIParams( memParams = AXIParams(
coherent = false,
addrBits = 64, addrBits = 64,
dataBits = 64), dataBits = 64,
lenBits = 8,
userBits = 1),
vcrParams = VCRParams(), vcrParams = VCRParams(),
vmeParams = VMEParams()) vmeParams = VMEParams())
}) })
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