Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
Y
yosys-tests
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
yosys-tests
Repository
00e5faef9d199b5d600da971dbb02cf52f220bd5
Switch branch/tag
yosys-tests
architecture
xilinx_ug901_synthesis_examples
History
Find file
Select Archive Format
Source code
Download zip
Download tar.gz
Download tar.bz2
Download tar
Fix some broken tests in xilinx_ug901_synthesis_examples
· fd707de0
Eddie Hung
committed
Feb 07, 2020
fd707de0
Name
Last commit
Last update
..
asym_ram_sdp_read_wider.v
Loading commit data...
asym_ram_sdp_write_wider.v
Loading commit data...
asym_ram_tdp_read_first.v
Loading commit data...
asym_ram_tdp_write_first.v
Loading commit data...
black_box_1.v
Loading commit data...
bytewrite_ram_1b.v
Loading commit data...
bytewrite_tdp_ram_nc.v
Loading commit data...
bytewrite_tdp_ram_readfirst2.v
Loading commit data...
bytewrite_tdp_ram_rf.v
Loading commit data...
bytewrite_tdp_ram_wf.v
Loading commit data...
cmacc.v
Loading commit data...
cmult.v
Loading commit data...
dynamic_shift_registers_1.v
Loading commit data...
dynpreaddmultadd.v
Loading commit data...
fsm_1.v
Loading commit data...
latches.v
Loading commit data...
macc.v
Loading commit data...
mult_unsigned.v
Loading commit data...
presubmult.v
Loading commit data...
ram_simple_dual_one_clock.v
Loading commit data...
ram_simple_dual_two_clocks.v
Loading commit data...
rams_dist.v
Loading commit data...
rams_init_file.data
Loading commit data...
rams_init_file.v
Loading commit data...
rams_pipeline.v
Loading commit data...
rams_sp_nc.v
Loading commit data...
rams_sp_rf.v
Loading commit data...
rams_sp_rf_rst.v
Loading commit data...
rams_sp_rom.v
Loading commit data...
rams_sp_rom_1.v
Loading commit data...
rams_sp_wf.v
Loading commit data...
rams_tdp_rf_rf.v
Loading commit data...
registers_1.v
Loading commit data...
sfir_shifter.v
Loading commit data...
shift_registers_0.v
Loading commit data...
shift_registers_1.v
Loading commit data...
squarediffmacc.v
Loading commit data...
squarediffmult.v
Loading commit data...
top_mux.v
Loading commit data...
tristates_1.v
Loading commit data...
tristates_2.v
Loading commit data...
xilinx_ug901_asym_ram_sdp_read_wider.ys
Loading commit data...
xilinx_ug901_asym_ram_sdp_write_wider.ys
Loading commit data...
xilinx_ug901_asym_ram_tdp_read_first.ys
Loading commit data...
xilinx_ug901_asym_ram_tdp_write_first.ys
Loading commit data...
xilinx_ug901_black_box_1.ys
Loading commit data...
xilinx_ug901_bytewrite_ram_1b.ys
Loading commit data...
xilinx_ug901_bytewrite_tdp_ram_nc.ys
Loading commit data...
xilinx_ug901_bytewrite_tdp_ram_readfirst2.ys
Loading commit data...
xilinx_ug901_bytewrite_tdp_ram_rf.ys
Loading commit data...
xilinx_ug901_bytewrite_tdp_ram_wf.ys
Loading commit data...
xilinx_ug901_cmacc.ys
Loading commit data...
xilinx_ug901_cmult.ys
Loading commit data...
xilinx_ug901_dynamic_shift_registers_1.ys
Loading commit data...
xilinx_ug901_dynpreaddmultadd.ys
Loading commit data...
xilinx_ug901_fsm_1.ys
Loading commit data...
xilinx_ug901_latches.ys
Loading commit data...
xilinx_ug901_macc.ys
Loading commit data...
xilinx_ug901_mult_unsigned.ys
Loading commit data...
xilinx_ug901_presubmult.ys
Loading commit data...
xilinx_ug901_ram_simple_dual_one_clock.ys
Loading commit data...
xilinx_ug901_ram_simple_dual_two_clocks.ys
Loading commit data...
xilinx_ug901_rams_dist.ys
Loading commit data...
xilinx_ug901_rams_init_file.ys
Loading commit data...
xilinx_ug901_rams_pipeline.ys
Loading commit data...
xilinx_ug901_rams_sp_nc.ys
Loading commit data...
xilinx_ug901_rams_sp_rf.ys
Loading commit data...
xilinx_ug901_rams_sp_rf_rst.ys
Loading commit data...
xilinx_ug901_rams_sp_rom.ys
Loading commit data...
xilinx_ug901_rams_sp_rom_1.ys
Loading commit data...
xilinx_ug901_rams_sp_wf.ys
Loading commit data...
xilinx_ug901_rams_tdp_rf_rf.ys
Loading commit data...
xilinx_ug901_registers_1.ys
Loading commit data...
xilinx_ug901_sfir_shifter.ys
Loading commit data...
xilinx_ug901_shift_registers_0.ys
Loading commit data...
xilinx_ug901_shift_registers_1.ys
Loading commit data...
xilinx_ug901_squarediffmacc.ys
Loading commit data...
xilinx_ug901_squarediffmult.ys
Loading commit data...
xilinx_ug901_top_mux.ys
Loading commit data...
xilinx_ug901_tristates_1.ys
Loading commit data...
xilinx_ug901_tristates_2.ys
Loading commit data...
xilinx_ug901_xilinx_ultraram_single_port_no_change.ys
Loading commit data...
xilinx_ug901_xilinx_ultraram_single_port_read_first.ys
Loading commit data...
xilinx_ug901_xilinx_ultraram_single_port_write_first.ys
Loading commit data...
xilinx_ultraram_single_port_no_change.v
Loading commit data...
xilinx_ultraram_single_port_read_first.v
Loading commit data...
xilinx_ultraram_single_port_write_first.v
Loading commit data...