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lvzhengyang
yosys-tests
Commits
fd707de0
Commit
fd707de0
authored
Feb 07, 2020
by
Eddie Hung
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Fix some broken tests in xilinx_ug901_synthesis_examples
parent
df36ec62
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4 changed files
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10 additions
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11 deletions
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-11
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys
+3
-4
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys
+1
-1
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys
+5
-5
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys
+1
-1
No files found.
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys
View file @
fd707de0
read_verilog ../cmult.v
hierarchy -top cmult
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
...
...
@@ -18,7 +17,7 @@ stat
select -assert-count 1 t:BUFG
select -assert-count 86 t:FDRE
select -assert-count 3 t:DSP48E1
select -assert-count
34
t:LUT2
select -assert-count
17
t:LUT2
select -assert-count 6 t:CARRY4
select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:CARRY4 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys
View file @
fd707de0
...
...
@@ -18,7 +18,7 @@ stat
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 1 t:DSP48E1
select -assert-count
32
t:LUT2
select -assert-count
16
t:LUT2
select -assert-count 9 t:LUT3
select -assert-count 6 t:CARRY4
...
...
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys
View file @
fd707de0
...
...
@@ -18,11 +18,11 @@ stat
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 4 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 12 t:LUT4
select -assert-count 25 t:LUT5
select -assert-count 32 t:LUT6
#
select -assert-count 4 t:LUT2
#
select -assert-count 3 t:LUT3
#
select -assert-count 12 t:LUT4
#
select -assert-count 25 t:LUT5
#
select -assert-count 32 t:LUT6
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys
View file @
fd707de0
...
...
@@ -18,7 +18,7 @@ stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 32 t:FDRE
select -assert-count
32
t:LUT2
select -assert-count
16
t:LUT2
select -assert-count 5 t:CARRY4
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:CARRY4 %% t:* %D
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