- 29 Jan, 2019 2 commits
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SergeyDegtyar committed
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MISC ===== Tasks in this group are just generating some output, so no traditional test bench could be made. Writing output from yosys and checking if result is expected is advised. 1.http://scratch.clifford.at/coverage_html/passes/tests/test_abcloop.cc.gcov.html This represents some internal tests for ABC loops 2. http://scratch.clifford.at/coverage_html/passes/tests/test_cell.cc.gcov.html note that you need to provide multiple tests in order to cover testing of all cell types. Also output should be checked if it contain "Fail" or "Error" in it 3. http://scratch.clifford.at/coverage_html/passes/cmds/torder.cc.gcov.html Use some verilog file, do proc and this should display you all cells in designed ordered. Require multiple different parameters to cover all. 4.http://scratch.clifford.at/coverage_html/passes/cmds/trace.cc.gcov.html loading verilog file and doing "trace proc" will create output with additional logs, not much to check from output to be honest 5. http://scratch.clifford.at/coverage_html/passes/cmds/write_file.cc.gcov.html just write to file and check if written output is fine 6. http://scratch.clifford.at/coverage_html/passes/cmds/stat.cc.gcov.html if you have liberty cell library files, try it with those specified. 7. http://scratch.clifford.at/coverage_html/passes/cmds/show.cc.gcov.html note that you would always need to set -viewer since you do not wish to call graphwiz. Need covering of various parameters on a reasonable complicated design to cover. 8. http://scratch.clifford.at/coverage_html/passes/cmds/scc.cc.gcov.html detection of logic loops, output needs to be tested in order to check if loop was detected on not. 9. http://scratch.clifford.at/coverage_html/passes/cmds/scatter.cc.gcov.html After doing synth on existing design, just run this step, can do opt_clean after and there should be lot of temporary and unused wires removed. 10. http://scratch.clifford.at/coverage_html/passes/cmds/rename.cc.gcov.html can load design and rename top modue, output should contain module with new name 11. http://scratch.clifford.at/coverage_html/passes/cmds/qwp.cc.gcov.html Use it on simple design since it takes a while on big ones. 12. http://scratch.clifford.at/coverage_html/passes/cmds/ltp.cc.gcov.html Check if returns expected value for your design 13. http://scratch.clifford.at/coverage_html/passes/cmds/edgetypes.cc.gcov.html it just outputs report, so not sure what would be valid to check, just execute for now. 14. http://scratch.clifford.at/coverage_html/passes/cmds/delete.cc.gcov.html load existing design and try removing inputs, outputs,... complete design 15. http://scratch.clifford.at/coverage_html/passes/cmds/cover.cc.gcov.html it just prints report, so nothing to check
SergeyDegtyar committed
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- 15 Jan, 2019 1 commit
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SergeyDegtyar committed
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- 02 Jan, 2019 1 commit
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5. clk2fflogic (104 - 144,180-195 are not covered) 9. memory_nordff(75-101 is not covered) 10. memory_unpack(91-108 is not covered) 12. hierarchy (the coverage from 44% increased to 61,3%)
SergeyDegtyar committed
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