Commits · 9d1a8df37240c402ae4bc6cd86e435c621b290ee · lvzhengyang / yosys-tests · GitLab

30 Oct, 2019 2 commits
- Rename test group back to 'architecture' · 743baf58
  SergeyDegtyar committed 5 years ago
  
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- Review and update tests for intel, sf2, xilinx, xilinx_ug901 architectures. · 73abab3b
  SergeyDegtyar committed 5 years ago
  
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28 Aug, 2019 1 commit
- Update synth_xilinx_srl to cope with BUFG · 6fd5fd38
  Eddie Hung committed 5 years ago
  
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24 Aug, 2019 1 commit
- Add some FDRE tests · 777f1dfb
  Eddie Hung committed 5 years ago
  
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