Update synth_xilinx_srl to cope with BUFG

architecture/synth_xilinx_srl/generate.py

@@ -24,7 +24,7 @@ def assert_static_area(fp, i, name):
     fp.write('''
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; cd {3}_{4}; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none";
+    wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; cd {3}_{4}; select t:BUFG t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none";
 endmodule
 `endif
 '''.format(fd, srl16, srl32, name, i))
@@ -62,7 +62,7 @@ def assert_dynamic_area(fp, i, name):
     fp.write('''
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; select t:MUXF7 -assert-count {3}; select t:MUXF8 -assert-count {4}; select t:LUT3 -assert-count {5}; select t:LUT5 -assert-count {6}; cd {7}_{8}; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT3 t:LUT5 %% %n t:* %i -assert-none";
+    wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; select t:MUXF7 -assert-count {3}; select t:MUXF8 -assert-count {4}; select t:LUT3 -assert-count {5}; select t:LUT5 -assert-count {6}; cd {7}_{8}; select t:BUFG t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT3 t:LUT5 %% %n t:* %i -assert-none";
 endmodule
 `endif
 '''.format(fd, srl16, srl32, muxf7, muxf8, lut3, lut5, name, i))

architecture/synth_xilinx_srl/rotate_3_fdre.v

@@ -2,7 +2,7 @@
 module rotate_3_fdre (input clk, output q);
 wire [2:0] r;
 FDRE #(.INIT(1'b1)) r0 (.C(clk), .CE(1'b1), .D(r[2]), .R(1'b0), .Q(r[0]));
-FDRE #(.INIT(1'b0)) r1 (.C(clk), .CE(1'b1), .D(r[0]), .R(1'b0), .Q(r[1]));
+FDRE #(.INIT(1'b0)) r1 (.C(clk), .CE(1'b1), .D(r[0]),           .Q(r[1]));
 FDRE #(.INIT(1'b0)) r2 (.C(clk), .CE(1'b1), .D(r[1]), .R(1'b0), .Q(r[2]));
 assign q = r[2];
 endmodule

architecture/synth_xilinx_srl/run-test.sh

@@ -20,8 +20,8 @@ if ! which iverilog > /dev/null ; then
 fi
 
 wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
-python3 generate_lfsr.py
-python3 ../generate.py
+#python3 generate_lfsr.py
+#python3 ../generate.py
 cp ../*.v .
 ${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="\
     -f 'verilog -noblackbox -icells' \

architecture/synth_xilinx_srl/test17a.v

@@ -17,6 +17,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test17a; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
+    wire [4095:0] assert_area = "cd test17a; select t:SRL16E -assert-count 1; select t:BUFG t:SRL16E %% %n t:* %i -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/test17b.v

@@ -10,6 +10,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test17b; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
+    wire [4095:0] assert_area = "cd test17b; select t:SRL16E -assert-count 1; select t:BUFG t:SRL16E %% %n t:* %i -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/test17c.v

@@ -12,6 +12,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test17c; select t:SRL16E -assert-count 2; select t:* t:SRL16E %d -assert-count 0;";
+    wire [4095:0] assert_area = "cd test17c; select t:SRL16E -assert-count 2; select t:BUFG t:SRL16E %% %n t:* %i -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/test17d.v

@@ -13,6 +13,7 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test17d; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:* t:SRL16E %d t:FD* %d -assert-count 0;";
+    wire [4095:0] assert_area = "cd test17d; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:BUFG t:SRL16E t:FD* %% %n t:* %i -assert-none";
+
 endmodule
 `endif

architecture/synth_xilinx_srl/test17e.v

@@ -15,6 +15,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test17e; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
+    wire [4095:0] assert_area = "cd test17e; select t:SRL16E -assert-count 1; select t:BUFG t:SRL16E %% %n t:* %i -assert-none;";
 endmodule
 `endif

architecture/synth_xilinx_srl/ug901a.v

@@ -21,6 +21,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd shift_registers_0; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
+    wire [4095:0] assert_area = "cd shift_registers_0; select t:SRLC32E -assert-count 1; select t:BUFG t:SRLC32E %% %n t:* %i -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/ug901b.v

@@ -26,6 +26,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd shift_registers_1; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
+    wire [4095:0] assert_area = "cd shift_registers_1; select t:SRLC32E -assert-count 1; select t:BUFG t:SRLC32E %% %n t:* %i -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/ug901c.v

@@ -21,6 +21,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd dynamic_shift_register_1; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
+    wire [4095:0] assert_area = "cd dynamic_shift_register_1; select t:SRLC32E -assert-count 1; select t:BUFG t:SRLC32E %% %n t:* %i -assert-none";
 endmodule
 `endif