backends
=======
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419

simple
=========
+ 1. passes/techmap/attrmap.cc
There is example in help block create example with
(* keep="true" *) attribute and run example

+ 2. passes/techmap/dff2dffe.cc
execute with  -unmap parameter

+ 3. passes/techmap/dff2dffs.cc

+ 4. passes/techmap/extract.cc
Lot of variations of input parameters is not excersised

? 5. passes/techmap/extract_counter.cc
This is specific to greenpak4 architecture, but idea is to have counter
in design and call this after synth_greenpak

+ 6. passes/techmap/shregmap.cc.
This also seams to be greenpak4 specific, but extracting shift register

misc
========
1. passes/techmap/insbuf.cc

Testing problems:
1. backends/firrtl/firrtl.cc – skipped because of error:
 ERROR: Unclocked write port 0 on memory top.ram.
Add model with memory block too, so you can cover line block starting at
line 419
2.dff2dffe -direct - skipped: ERROR: Found error in internal cell
\dffe.$procdff$47 ($dffe) at
3.insbuf -buf $_BUF_ in out - skipped: ERROR: Found error in internal
cell

IV frontends
=============

For frontends idea is that you do not do read_verilog but some you are
reading input in different format.
Since most of formats yosys can also read and write you can use plain
verilog write blif for example
and use that as source for this coverage. For liberty files many
examples can be found so that is also in list of tasks

1.
http://scratch.clifford.at/coverage_html/frontends/blif/blifparse.cc.gcov.html
2.
http://scratch.clifford.at/coverage_html/frontends/ilang/ilang_frontend.cc.gcov.html
3.
http://scratch.clifford.at/coverage_html/frontends/json/jsonparse.cc.gcov.html
4.
http://scratch.clifford.at/coverage_html/frontends/liberty/liberty.cc.gcov.html