Add tests for commits:
- Add "wreduce -keepdc";
- Add "fmcombine -initeq -anyeq";
- Add "stat -tech xilinx";
- Add "synth_xilinx -arch".

Add new tests to backends and architecture;
Merge commit "Add regression test for Yosys PR 896"

1. Add tests for synth_anlogic command
Now this tests are commented because of:
+ iverilog -o testbench ../testbench.v synth.v ../../common.v
../../../../../techlibs/common/simcells.v
../../../../../techlibs/anlogic/cells_sim.v
../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to bind
wire/reg/memory `A' in `testbench.uut._09_'
../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to
elaborate r-value: (INIT)>>(A)
2 error(s) during elaboration.

2. Add 'regression' test