Add tests to 'simple' (Expand coverage for memory_* commands)

simple/Makefile

@@ -92,6 +92,7 @@ $(eval $(call template,aigmap,aigmap aigmap_nand))
 
 #memory_memx, memory_nordff(75-101 not covered), memory_unpack(91-108 not covered)
 $(eval $(call template,memory,memory memory_memx memory_nordff memory_unpack memory_nomap memory_nordff_opt memory_memx_opt memory_bram_opt memory_share))
+$(eval $(call template,memory_single_port,memory memory_memx memory_nordff memory_unpack memory_nomap memory_nordff_opt memory_memx_opt memory_bram_opt memory_share))
 $(eval $(call template_error,memory_bram_error, memory_bram_syntax_error_in_rules memory_bram_cant_open_rules_file ))
 
 #uniquify

simple/memory_single_port/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [7:0] data_a = 0;
+	reg [7:0] data_b = 0;
+	reg [5:0] addr_a = 0;
+	reg [5:0] addr_b = 0;
+    reg we_a = 0;
+	reg we_b = 1;
+    reg re_a = 1;
+	reg re_b = 1;
+	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.data_b(data_b),
+	.addr_a(addr_a),
+	.addr_b(addr_b),
+	.we_a(we_a),
+	.we_b(we_b),
+	.re_a(re_a),
+	.re_b(re_b),
+	.clk(clk),
+	.q_a(q_a),
+	.q_b(q_b)
+    );
+
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;
+    data_b <= data_b + 5;
+
+    addr_a <= addr_a + 1;
+    addr_b <= addr_b + 1;
+    end
+
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a;
+    we_b <= !we_b;
+    end
+
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    //uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
+
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/memory_single_port/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		q_a <= ram[addr_a];
+`else
+		if (we_a)
+		begin
+			ram[addr_a] <= 8'bXXXXXXXX;
+			q_a <= 8'bXXXXXXXX;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+`endif
+	end
+
+
+
+endmodule

simple/memory_single_port/words.v

+

simple/run.sh

@@ -175,7 +175,8 @@ else
 			elif [ "$1" = "macc" ]; then
 				expected_string="cell \$macc"
 				expected="0"
-			elif [ "$1" = "memory" ]; then
+			elif [ "$1" = "memory" ] ||
+				[ "$1" = "memory_single_port" ]; then
 				expected_string="cell \$mem "
 				expected="0"
 			elif [ "$1" = "muxcover" ] ||\

simple/scripts/memory_nordff.ys

 read_verilog ../top.v
+memory_nordff
 proc
 memory_nordff
 memory_dff
+memory_nordff
 opt_clean
+memory_nordff
 memory_share
+memory_nordff
 opt_clean
+memory_nordff
 memory_collect
+memory_nordff
 memory_map
+memory_nordff
+memory_unpack
 tee -o result.log dump
 design -reset
 read_verilog ../top.v

simple/scripts/memory_share.ys

 read_verilog ../top.v
 proc
 memory_share
+memory_dff
+memory_share
+opt_clean
+memory_share
+memory_nordff
+opt_clean
+memory_share
+memory_collect
+memory_share
+memory_nordff
+memory_share
+memory_map
+memory_share
 memory
 memory_share
 tee -o result.log dump

simple/scripts/memory_unpack.ys

 read_verilog ../top.v
 proc
+memory_unpack
 memory_collect
+memory_unpack
 memory_memx
 memory_unpack
+memory
+memory_unpack
 tee -o result.log dump
 design -reset
 read_verilog ../top.v