Add tests to 'misc'

tests for 'onehot';
tests for 'pmux2shiftx';
tests for 'wblif'.

misc/Makefile

@@ -231,4 +231,16 @@ $(eval $(call template,pmuxtree, pmuxtree))
 #opt_rmdff_sat
 $(eval $(call template,opt_rmdff_sat, opt_rmdff_sat))
 
+#wbflip
+$(eval $(call template,wbflip, wbflip wbflip_top))
+
+#pmux2shiftx
+$(eval $(call template,pmux2shiftx, pmux2shiftx_norange pmux2shiftx_onehot_shiftx pmux2shiftx_onehot_pmux pmux2shiftx_onehot_ignore pmux2shiftx_min_choices_0 pmux2shiftx_min_choices_3000 pmux2shiftx_min_dens_3000 pmux2shiftx_min_dens_0 pmux2shiftx_vv pmux2shiftx_v pmux2shiftx_top pmux2shiftx ))
+$(eval $(call template,pmux2shiftx_2, pmux2shiftx_norange pmux2shiftx_onehot_shiftx pmux2shiftx_onehot_pmux pmux2shiftx_onehot_ignore pmux2shiftx_min_choices_0 pmux2shiftx_min_choices_3000 pmux2shiftx_min_dens_3000 pmux2shiftx_min_dens_0 pmux2shiftx_vv pmux2shiftx_v pmux2shiftx_top pmux2shiftx ))
+$(eval $(call template,pmux2shiftx_fsm, pmux2shiftx_norange pmux2shiftx_onehot_shiftx pmux2shiftx_onehot_pmux pmux2shiftx_onehot_ignore pmux2shiftx_min_choices_0 pmux2shiftx_min_choices_3000 pmux2shiftx_min_dens_3000 pmux2shiftx_min_dens_0 pmux2shiftx_vv pmux2shiftx_v pmux2shiftx_top pmux2shiftx ))
+
+#onehot
+$(eval $(call template,onehot, onehot onehot_v onehot_vv ))
+
+
 .PHONY: all clean

misc/onehot/top.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

misc/pmux2shiftx/top.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

misc/pmux2shiftx_2/top.v

+module top(input [7:0] i, output o);
+always @*
+case (i[6:3])
+    4: o <= i[0];
+    3: o <= i[2];
+    7: o <= i[3];
+    default: o <= 1'b0;
+endcase
+endmodule

misc/pmux2shiftx_fsm/top.v

+ module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1      
+ );
+ input   clock,reset,req_0,req_1;
+ output  gnt_0,gnt_1;
+ wire    clock,reset,req_0,req_1;
+ reg     gnt_0,gnt_1;
+ 
+ parameter SIZE = 3           ;
+ parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+ 
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+ 
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+   state <=  #1  IDLE;
+   gnt_0 <= 0;
+   gnt_1 <= 0;
+ end else
+  case(state)
+    IDLE : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+`ifndef BUG        
+                 gnt_0 <= 1;
+`else
+                 gnt_0 <= 1'bZ;
+`endif
+               end else if (req_1 == 1'b1) begin
+                 gnt_1 <= 1;
+                 state <=  #1  GNT0;
+               end else begin
+                 state <=  #1  IDLE;
+               end
+    GNT0 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+               end else begin
+                 gnt_0 <= 0;
+                 state <=  #1  IDLE;
+               end
+    GNT1 : if (req_1 == 1'b1) begin
+                 state <=  #1  GNT2;
+				 gnt_1 <= req_0;
+               end
+    GNT2 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT1;
+				 gnt_1 <= req_1;
+               end 
+    default : state <=  #1  IDLE;
+ endcase
+ end
+ 
+ endmodule
+ 
+ module top (
+input clk,
+input rst,
+input a,
+input b,
+output g0,
+output g1
+);
+
+fsm u_fsm ( .clock(clk),
+            .reset(rst), 
+            .req_0(a), 
+            .req_1(b), 
+            .gnt_0(g0), 
+            .gnt_1(g1));
+
+endmodule

misc/run.sh

@@ -514,6 +514,12 @@ else
 	elif [ "$2" = "pmuxtree" ]; then
 		expected_string="cell \$pmux"
 		expected="0"
+	elif [ "$1" = "pmux2shiftx" ]; then
+		if [ "$2" = "pmux2shiftx_min_choices_3000" ] || \
+		   [ "$2" = "pmux2shiftx_min_dens_3000" ]; then
+		   expected="0"
+		fi
+		expected_string="cell \$shiftx"
 	elif [ "$1" = "qwp" ]; then
 		expected_string="attribute \\\qwp_position"
 	elif [ "$2" = "rename" ]; then

misc/scripts/onehot.ys

+read_verilog ../top.v
+proc
+pmux2shiftx
+onehot
+tee -o result.log dump

misc/scripts/onehot_v.ys

+read_verilog ../top.v
+proc
+pmux2shiftx
+onehot -v
+tee -o result.log dump

misc/scripts/onehot_vv.ys

+read_verilog ../top.v
+proc
+pmux2shiftx
+onehot -vv
+tee -o result.log dump

misc/scripts/pmux2shiftx.ys

+read_verilog ../top.v
+proc
+pmux2shiftx
+tee -o result.log dump

misc/scripts/pmux2shiftx_min_choices_0.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -min_choices 0
+onehot
+tee -o result.log dump

misc/scripts/pmux2shiftx_min_choices_3000.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -min_choices 3000
+tee -o result.log dump

misc/scripts/pmux2shiftx_min_dens_0.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -min_density 0
+onehot
+tee -o result.log dump

misc/scripts/pmux2shiftx_min_dens_3000.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -min_density 3000
+tee -o result.log dump

misc/scripts/pmux2shiftx_norange.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -norange
+onehot
+tee -o result.log dump

misc/scripts/pmux2shiftx_onehot_ignore.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -onehot ignore
+onehot
+tee -o result.log dump

misc/scripts/pmux2shiftx_onehot_pmux.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -onehot pmux
+tee -o result.log dump

misc/scripts/pmux2shiftx_onehot_shiftx.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -onehot shiftx
+onehot
+tee -o result.log dump

misc/scripts/pmux2shiftx_top.ys

+read_verilog ../top.v
+proc
+pmux2shiftx top
+tee -o result.log dump

misc/scripts/pmux2shiftx_v.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -v
+tee -o result.log dump

misc/scripts/pmux2shiftx_vv.ys

+read_verilog ../top.v
+proc
+pmux2shiftx -vv
+tee -o result.log dump

misc/scripts/wbflip.ys

+read_verilog ../top.v
+proc
+tee -o result.log wbflip

misc/scripts/wbflip_top.ys

+read_verilog ../top.v
+proc
+tee -o result.log wbflip top

misc/wbflip/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule