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lvzhengyang
yosys-tests
Commits
fdaf7677
Commit
fdaf7677
authored
Mar 15, 2019
by
Eddie Hung
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parent
c4152912
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8 changed files
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448 additions
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280 deletions
+448
-280
architecture/run.sh
+2
-2
architecture/synth_xilinx_srl/test1.ys
+130
-131
architecture/synth_xilinx_srl/test10.ys
+151
-0
architecture/synth_xilinx_srl/test6.ys
+130
-130
architecture/synth_xilinx_srl/test7.ys
+1
-1
architecture/synth_xilinx_srl/test9.ys
+1
-1
architecture/synth_xilinx_srl/testbench.v
+4
-0
architecture/synth_xilinx_srl/top.v
+29
-15
No files found.
architecture/run.sh
View file @
fdaf7677
...
...
@@ -68,8 +68,8 @@ elif [ "$1" = "synth_xilinx_srl" ]; then
iverilog
-DTEST8
synth8.v
-o
testbench ../testbench.v
-I
.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog
-DTEST9
synth9.v
-o
testbench ../testbench.v
-I
.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
#
run
#
iverilog -DTEST10 synth10.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog
-DTEST10
synth10.v
-o
testbench ../testbench.v
-I
.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif
[
"
$1
"
=
"synth_greenpak4"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
else
...
...
architecture/synth_xilinx_srl/test1.ys
View file @
fdaf7677
...
...
@@ -4,134 +4,133 @@ rename -top synth
clean -purge
write_verilog synth1.v
cd $paramod\shift_reg\depth=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=2; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=3; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=4; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=5; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=6; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=7; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=8; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=9; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=10; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=11; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=12; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=13; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=14; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=15; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=16; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=17; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=18; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=19; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=20; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=21; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=22; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=23; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=24; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=25; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=26; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=27; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=28; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=29; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=30; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=31; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=32; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=33; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=34; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=35; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=36; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=37; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=38; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=39; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=40; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=41; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=42; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=43; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=44; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=45; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=46; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=47; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=48; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=49; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=50; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=51; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=52; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=53; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=54; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=55; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=56; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=57; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=58; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=59; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=60; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=61; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=62; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=63; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=64; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=65; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=66; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=67; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=68; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=69; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=70; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=71; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=72; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=73; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=74; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=75; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=76; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=77; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=78; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=79; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=80; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=81; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=82; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=83; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=84; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=85; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=86; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=87; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=88; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=89; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=90; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=91; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=92; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=93; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=94; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=95; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=96; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=97; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=98; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=99; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=100; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=101; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=102; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=103; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=104; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=105; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=106; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=107; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=108; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=109; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=110; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=111; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=112; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=113; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=114; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=115; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=116; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=117; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=118; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=119; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=120; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=121; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=122; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=123; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=124; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=125; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=126; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=127; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=128; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=129; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=130; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\shift_reg\depth=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=2; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=3; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=4; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=5; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=6; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=7; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=8; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=9; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=10; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=11; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=12; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=13; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=14; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=15; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=16; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=17; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=18; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=19; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=20; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=21; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=22; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=23; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=24; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=25; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=26; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=27; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=28; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=29; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=30; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=31; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=32; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=33; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=34; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=35; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=36; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=37; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=38; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=39; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=40; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=41; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=42; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=43; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=44; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=45; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=46; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=47; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=48; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=49; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=50; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=51; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=52; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=53; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=54; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=55; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=56; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=57; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=58; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=59; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=60; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=61; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=62; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=63; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=64; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=65; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=66; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=67; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=68; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=69; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=70; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=71; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=72; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=73; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=74; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=75; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=76; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=77; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=78; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=79; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=80; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=81; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=82; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=83; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=84; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=85; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=86; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=87; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=88; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=89; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=90; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=91; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=92; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=93; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=94; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=95; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=96; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=97; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=98; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=99; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=100; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=101; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=102; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=103; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=104; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=105; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=106; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=107; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=108; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=109; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=110; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=111; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=112; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=113; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=114; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=115; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=116; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=117; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=118; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=119; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=120; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=121; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=122; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=123; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=124; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=125; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=126; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=127; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=128; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=129; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd $paramod\shift_reg\depth=130; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test10.ys
0 → 100644
View file @
fdaf7677
read_verilog -icells -DTEST10 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog -norename synth10.v
#cd $paramod\shift_reg\depth=1\fixed_length=0; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=2\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=3\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=4\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=5\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=6\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=7\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=8\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=9\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=10\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=11\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=12\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=13\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=14\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=15\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=16\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=17\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=18\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=19\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=20\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=21\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=22\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=23\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=24\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=25\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=26\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=27\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=28\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=29\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=30\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=31\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=32\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=33\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=34\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=35\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=36\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=37\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=38\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=39\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=40\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=41\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=42\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=43\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=44\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=45\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=46\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=47\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=48\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=49\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=50\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=51\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=52\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=53\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=54\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=55\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=56\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=57\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=58\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=59\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=60\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=61\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=62\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=63\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=64\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=65\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=66\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=67\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=68\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=69\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=70\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=71\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=72\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=73\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=74\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=75\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=76\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=77\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=78\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=79\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=80\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=81\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=82\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=83\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=84\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=85\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=86\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=87\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=88\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=89\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=90\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=91\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=92\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=93\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=94\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=95\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=96\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=97\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=98\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=99\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=100\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=101\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=102\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=103\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=104\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=105\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=106\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=107\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=108\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=109\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=110\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=111\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=112\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=113\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=114\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=115\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=116\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=117\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=118\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=119\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=120\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=121\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=122\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=123\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=124\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=125\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=126\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=127\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=128\fixed_length=0; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
#
#cd $paramod\shift_reg\depth=129\fixed_length=0; select t:FD* -assert-count 129; select t:FD* t:LUT* t:MUX* t:XORCY %% %n t:* %i -assert-none
#cd $paramod\shift_reg\depth=130\fixed_length=0; select t:FD* -assert-count 130; select t:FD* t:LUT* t:MUX* t:XORCY %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test6.ys
View file @
fdaf7677
...
...
@@ -4,133 +4,133 @@ rename -top synth
clean -purge
write_verilog synth6.v
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=2; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=3; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=4; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=5; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=6; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=7; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=8; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=9; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=10; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=11; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=12; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=13; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=14; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=15; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=16; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=17; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=18; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=19; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=20; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=21; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=22; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=23; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=24; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=25; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=26; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=27; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=28; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=29; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=30; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=31; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=32; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=33; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=34; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=35; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=36; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=37; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=38; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=39; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=40; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=41; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=42; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=43; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=44; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=45; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=46; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=47; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=48; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=49; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=50; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=51; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=52; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=53; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=54; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=55; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=56; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=57; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=58; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=59; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=60; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=61; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=62; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=63; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=64; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=65; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=66; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=67; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=68; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=69; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=70; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=71; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=72; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=73; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=74; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=75; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=76; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=77; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=78; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=79; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=80; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=81; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=82; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=83; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=84; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=85; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=86; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=87; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=88; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=89; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=90; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=91; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=92; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=93; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=94; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=95; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=96; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=97; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=98; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=99; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=100; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=101; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=102; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=103; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=104; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=105; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=106; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=107; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=108; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=109; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=110; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=111; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=112; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=113; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=114; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=115; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=116; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=117; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=118; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=119; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=120; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=121; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=122; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=123; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=124; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=125; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=126; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=127; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=128; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=129; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=130; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n
%i -assert-none
cd $paramod\shift_reg\
depth=1\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=2\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=3\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=4\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=5\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=6\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=7\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=8\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=9\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=10\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=11\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=12\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=13\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=14\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=15\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=16\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=17\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=18\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=19\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=20\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=21\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=22\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=23\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=24\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=25\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=26\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=27\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=28\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=29\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=30\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=31\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=32\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=33\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=34\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=35\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=36\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=37\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=38\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=39\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=40\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=41\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=42\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=43\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=44\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=45\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=46\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=47\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=48\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=49\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=50\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=51\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=52\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=53\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=54\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=55\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=56\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=57\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=58\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=59\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=60\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=61\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=62\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=63\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=64\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=65\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=66\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=67\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=68\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=69\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=70\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=71\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=72\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=73\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=74\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=75\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=76\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=77\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=78\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=79\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=80\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=81\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=82\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=83\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=84\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=85\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=86\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=87\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=88\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=89\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=90\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=91\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=92\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=93\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=94\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=95\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=96\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=97\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=98\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=99\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=100\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=101\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=102\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=103\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=104\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=105\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=106\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=107\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=108\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=109\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=110\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=111\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=112\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=113\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=114\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=115\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=116\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=117\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=118\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=119\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=120\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=121\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=122\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=123\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=124\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=125\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=126\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=127\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=128\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=129\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
cd $paramod\shift_reg\
depth=130\inferred=1\init=1\neg_clk=1; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:*
%i -assert-none
architecture/synth_xilinx_srl/test7.ys
View file @
fdaf7677
...
...
@@ -6,4 +6,4 @@ write_verilog synth7.v
# Check that shift registers with resets are not inferred into SRLs
cd $paramod\shift_reg\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
cd $paramod\shift_reg\
inferred=1\init=1\neg_clk=1\depth=13
1\er_is_reset=1; select t:SRL* -assert-count 0
cd $paramod\shift_reg\
depth=131\inferred=1\init=1\neg_clk=
1\er_is_reset=1; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/test9.ys
View file @
fdaf7677
...
...
@@ -5,4 +5,4 @@ clean -purge
write_verilog synth9.v
# Check that wide shift registers are not a problem
cd $paramod\shift_reg\width=131\
inferred=1\init=1\neg_clk=1\depth=13
1; select t:FD* -assert-count 0
cd $paramod\shift_reg\width=131\
depth=131\inferred=1\init=1\neg_clk=
1; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/testbench.v
View file @
fdaf7677
...
...
@@ -18,6 +18,7 @@ module testbench;
reg
[
`N
-
1
:
0
]
a
;
reg
e
,
r
;
reg
[$
clog2
(
`N
)
-
1
:
0
]
l
;
wire
[
`N
-
1
:
0
]
y
;
wire
[
`N
-
1
:
0
]
z
;
...
...
@@ -26,6 +27,7 @@ module testbench;
.
a
(
a
)
,
.
e
(
e
)
,
.
r
(
r
)
,
.
l
(
l
)
,
.
z
(
y
)
)
;
...
...
@@ -34,12 +36,14 @@ module testbench;
.
a
(
a
)
,
.
e
(
e
)
,
.
r
(
r
)
,
.
l
(
l
)
,
.
z
(
z
)
)
;
always
@
(
negedge
clk
)
begin
e
<=
$
random
;
r
<=
$
random
;
l
<=
$
random
;
end
generate
...
...
architecture/synth_xilinx_srl/top.v
View file @
fdaf7677
`include
"defines.vh"
module
top
(
input
clk
,
input
[
`N
-
1
:
0
]
a
,
input
e
,
r
,
output
[
`N
-
1
:
0
]
z
)
;
module
top
(
input
clk
,
input
[
`N
-
1
:
0
]
a
,
input
e
,
r
,
input
[$
clog2
(
`N
)
-
1
:
0
]
l
,
output
[
`N
-
1
:
0
]
z
)
;
generate
genvar
i
;
`ifdef
TEST1
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
pos_clk_no_enable_no_init_not_inferred
shift_reg
#(
.
depth
(
i
+
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
/*l*/
,
z
[
i
])
;
end
`elsif
TEST2
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
pos_clk_with_enable_no_init_not_inferred
shift_reg
#(
.
depth
(
i
+
1
))
sr
(
clk
,
a
[
i
]
,
e
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
))
sr
(
clk
,
a
[
i
]
,
e
,
/*l*/
,
z
[
i
])
;
end
`elsif
TEST3
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
pos_clk_with_enable_with_init_inferred
shift_reg
#(
.
depth
(
i
+
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
sr
(
clk
,
a
[
i
]
,
e
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
sr
(
clk
,
a
[
i
]
,
e
,
/*l*/
,
z
[
i
])
;
end
`elsif
TEST4
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
neg_clk_no_enable_no_init_not_inferred
shift_reg
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
/*l*/
,
z
[
i
])
;
end
`elsif
TEST5
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
neg_clk_no_enable_no_init_inferred
shift_reg
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
/*l*/
,
z
[
i
])
;
end
`elsif
TEST6
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
neg_clk_with_enable_with_init_inferred
shift_reg
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
sr
(
clk
,
a
[
i
]
,
e
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
sr
(
clk
,
a
[
i
]
,
e
,
/*l*/
,
z
[
i
])
;
end
`elsif
TEST7
// Check that use of resets block shreg
(
*
keep
*
)
shift_reg
#(
.
depth
(
`N
)
,
.
er_is_reset
(
1
))
pos_clk_no_enable_no_init_not_inferred_with_reset
(
clk
,
a
[
1
]
,
r
,
z
[
0
])
;
shift_reg
#(
.
depth
(
`N
)
,
.
er_is_reset
(
1
))
pos_clk_no_enable_no_init_not_inferred_with_reset
(
clk
,
a
[
1
]
,
r
,
/*l*/
,
z
[
0
])
;
(
*
keep
*
)
shift_reg
#(
.
depth
(
`N
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
)
,
.
er_is_reset
(
1
))
neg_clk_no_enable_with_init_with_inferred_with_reset
(
clk
,
a
[
2
]
,
r
,
FIXME
/*z[1]*/
)
;
shift_reg
#(
.
depth
(
`N
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
)
,
.
er_is_reset
(
1
))
neg_clk_no_enable_with_init_with_inferred_with_reset
(
clk
,
a
[
2
]
,
r
,
/*l*/
,
FIXME
/*z[1]*/
)
;
assign
z
[
`N
-
1
:
2
]
=
'b0
;
// Suppress no driver warning
`elsif
TEST8
// Check multi-bit works
(
*
keep
*
)
shift_reg
#(
.
depth
(
`N
)
,
.
width
(
`N
))
pos_clk_no_enable_no_init_not_inferred_N_width
(
clk
,
a
,
r
,
z
)
;
shift_reg
#(
.
depth
(
`N
)
,
.
width
(
`N
))
pos_clk_no_enable_no_init_not_inferred_N_width
(
clk
,
a
,
r
,
/*l*/
,
z
)
;
`elsif
TEST9
(
*
keep
*
)
shift_reg
#(
.
depth
(
`N
)
,
.
width
(
`N
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
neg_clk_no_enable_with_init_with_inferred_N_width
(
clk
,
a
,
r
,
z
)
;
shift_reg
#(
.
depth
(
`N
)
,
.
width
(
`N
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
neg_clk_no_enable_with_init_with_inferred_N_width
(
clk
,
a
,
r
,
/*l*/
,
z
)
;
`elsif
TEST10
for
(
i
=
1
;
i
<
`N
;
i
=
i
+
1
)
begin
:
neg_clk_with_enable_with_init_inferred
shift_reg
#(
.
depth
(
i
+
1
)
,
.
fixed_length
(
0
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
l
[$
clog2
(
i
+
1
)
-
1
:
0
]
,
z
[
i
])
;
end
assign
z
[
0
]
=
'b0
;
// Suppress no driver warning
`endif
endgenerate
endmodule
module
shift_reg
#(
parameter
width
=
1
)
(
input
clk
,
input
[
width
-
1
:
0
]
a
,
input
er
,
output
[
width
-
1
:
0
]
z
)
;
module
shift_reg
#(
parameter
width
=
1
,
depth
=
1
)
(
input
clk
,
input
[
width
-
1
:
0
]
a
,
input
er
,
input
[$
clog2
(
depth
)
-
1
:
0
]
l
,
output
[
width
-
1
:
0
]
z
)
;
parameter
inferred
=
0
;
parameter
init
=
0
;
parameter
neg_clk
=
0
;
parameter
depth
=
1
;
parameter
er_is_reset
=
0
;
parameter
fixed_length
=
depth
;
generate
if
(
inferred
==
0
)
begin
wire
[
depth
:
0
]
int
[
width
-
1
:
0
]
;
genvar
j
;
for
(
j
=
0
;
j
<
width
;
j
=
j
+
1
)
begin
wire
[
depth
-
1
:
0
]
w
;
assign
int
[
j
][
0
]
=
a
[
j
]
;
genvar
i
;
for
(
i
=
0
;
i
<
depth
;
i
=
i
+
1
)
begin
...
...
@@ -72,7 +77,13 @@ generate
else
\
$
_
DFF_PP0_
r
(
.
C
(
clk
)
,
.
D
(
int
[
j
][
i
])
,
.
R
(
er
)
,
.
Q
(
int
[
j
][
i
+
1
]))
;
end
assign
z
[
j
]
=
int
[
j
][
depth
]
;
if
(
fixed_length
>
0
)
assign
z
[
j
]
=
int
[
j
][
fixed_length
]
;
else
begin
//assign z[j] = int[j][l+1];
assign
w
=
int
[
j
][
depth
:
1
]
;
assign
z
[
j
]
=
w
[
l
]
;
end
end
end
else
begin
...
...
@@ -122,7 +133,10 @@ generate
always
@
(
posedge
clk
or
posedge
er
)
if
(
er
)
int
[
j
]
<=
'b0
;
else
int
[
j
]
<=
{
int
[
j
][
depth
-
2
:
0
]
,
a
[
j
]
};
end
end
assign
z
[
j
]
=
int
[
j
][
depth
-
1
]
;
if
(
fixed_length
>
0
)
assign
z
[
j
]
=
int
[
j
][
fixed_length
-
1
]
;
else
assign
z
[
j
]
=
int
[
j
][
l
]
;
end
end
end
...
...
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