Commit df36ec62 by Eddie Hung

Fix failing architecture.synth_xilinx* tests

parent 2c0a8ebf
read_verilog ../top_dsp_simd.v
design -save read
hierarchy -top simd
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd simd # Constrain all select calls below inside the top module
stat
select -assert-count 3 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D
read_verilog ../top_nocarry.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:LUT2
select -assert-count 3 t:LUT4
select -assert-count 4 t:LUT6
select -assert-count 2 t:CARRY4
select -assert-none t:LUT2 t:LUT4 t:LUT6 t:CARRY4 %% t:* %D
select -assert-none t:LUT* t:CARRY4 %% t:* %D
design -load read
hierarchy -top top
proc
design -load preopt
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nocarry -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4
select -assert-count 4 t:LUT6
select -assert-none t:LUT2 t:LUT4 t:LUT6 %% t:* %D
select -assert-none t:CARRY4
select -assert-none t:LUT* %% t:* %D
read_verilog ../top_dsp.v
design -save read
read_verilog ../top_nowidelut.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -noiopad # equivalency check
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 12 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 6 t:LUT4
select -assert-count 1 t:LUT5
select -assert-count 33 t:LUT6
select -assert-count 3 t:CARRY4
select -assert-count 1 t:MUXF7
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:CARRY4 t:MUXF7 %% t:* %D
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT* t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut -noiopad # equivalency check
design -load preopt
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nowidelut -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 10 t:LUT2
select -assert-count 6 t:LUT3
select -assert-count 5 t:LUT4
select -assert-count 2 t:LUT5
select -assert-count 32 t:LUT6
select -assert-count 3 t:CARRY4
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:CARRY4 %% t:* %D
select -assert-none t:MUXF7
select -assert-none t:MUXF8
select -assert-none t:LUT* t:MUXF7 t:MUXF8 %% t:* %D
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment