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yosys-tests
Commit f200dc81 by SergeyDegtyar
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Remove unnecessary output files generation

parent 9c8c9592
Showing with 274 additions and 318 deletions
simple_reviewed/alu/gates.ys
read_verilog ../top.v
synth -top top
abc -g gates
stat
select -assert-count 98 t:$_ANDNOT_
select -assert-count 465 t:$_AND_
select -assert-count 32 t:$_DFF_P_
......
simple_reviewed/alu/luts.ys
read_verilog ../top.v
synth -top top
abc -lut 4
stat
select -assert-count 32 t:$_DFF_P_
select -assert-count 689 t:$lut
simple_reviewed/design_import/design_import.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
design -save top
design -import top
write_verilog synth.v
simple_reviewed/design_import/design_import_as.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
design -save top
design -import top -as top_new
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap.ys
......@@ -2,11 +2,11 @@ read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap
tee -o result.log dump
dump
synth -top top
dff2dffe
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_direct.ys
......@@ -3,11 +3,11 @@ proc
dff2dffe
dff2dffe -direct $dff $dffe
dff2dffe -unmap
tee -o result.log dump
dump
synth -top top
dff2dffe -direct $_DFF_P_ $_DFFE_PP_
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_direct_match.ys
......@@ -6,4 +6,4 @@ dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_mince.ys
......@@ -2,11 +2,11 @@ read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap-mince 2
tee -o result.log dump
dump
synth -top top
dff2dffe
dff2dffe -unmap-mince 2
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dffsr2dff/dffsr2dff.ys
......@@ -11,4 +11,4 @@ flatten
opt
opt_rmdff
dffsr2dff
write_verilog synth.v
simple_reviewed/expose/expose_cut.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -cut
write_verilog synth.v
simple_reviewed/expose/expose_dff.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_dff_dff.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_dff_dffr.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_evert.ys
......@@ -8,4 +8,4 @@ flatten
opt
opt_rmdff
expose -evert
write_verilog synth.v
simple_reviewed/expose/expose_evert_dff.ys
......@@ -8,4 +8,4 @@ flatten
opt
opt_rmdff
expose -evert-dff
write_verilog synth.v
simple_reviewed/expose/expose_evert_dff_shared.ys
......@@ -10,4 +10,4 @@ expose -evert-dff
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/expose/expose_evert_shared.ys
......@@ -6,4 +6,4 @@ opt
opt_rmdff
expose -evert -shared
expose -shared -evert
write_verilog synth.v
simple_reviewed/expose/expose_input.ys
......@@ -9,4 +9,4 @@ expose -input
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/expose/expose_sep.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -sep |
write_verilog synth.v
simple_reviewed/expose/expose_shared.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -shared
write_verilog synth.v
simple_reviewed/extract/extract_cell_attr.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -cell_attr attr
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_compat.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -compat $dff a
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_constports.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -constports
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_ignore_param.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -ignore_param $dff param
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_ignore_parameters.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -ignore_parameters
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_map.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_map_design.ys
......@@ -4,4 +4,4 @@ extract -map %top_test
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_mine.ys
read_verilog ../top.v
extract -mine out.ilang
write_verilog synth.v
simple_reviewed/extract/extract_mine_cells_span.ys
read_verilog ../top.v
extract -mine out.ilang -mine_cells_span 3 5
write_verilog synth.v
simple_reviewed/extract/extract_mine_limit_matches_per_module.ys
read_verilog ../top.v
extract -mine out.ilang -mine_limit_matches_per_module 5
write_verilog synth.v
simple_reviewed/extract/extract_mine_max_fanout.ys
read_verilog ../top.v
extract -mine out.ilang -mine_max_fanout 2
write_verilog synth.v
simple_reviewed/extract/extract_mine_min_freq.ys
read_verilog ../top.v
extract -mine out.ilang -mine_min_freq 10
write_verilog synth.v
simple_reviewed/extract/extract_mine_split.ys
read_verilog ../top.v
extract -mine out.ilang -mine_split 2 2
write_verilog synth.v
simple_reviewed/extract/extract_nodefaultswaps.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -nodefaultswaps
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_perm.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -perm $dff D,CLK D,CLK
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_swap.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -swap $dff D,CLK
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_verbose.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -verbose
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_wire_attr.ys
......@@ -3,4 +3,4 @@ extract -map ../top.v -wire_attr attr
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_down.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_maxwidth.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter -maxwidth 4
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_pout.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter -pout X
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_pout_without_args_fail.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
extract_counter -pout
design -reset
read_verilog ../top_err.v
write_verilog synth.v
simple_reviewed/flowmap/flowmap.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
synth -top top
flowmap
select -assert-any t:$lut
write_verilog synth.v
simple_reviewed/flowmap/flowmap_cells.ys
read_verilog ../top.v
synth -top top
flowmap -cells $dff top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_debug.ys
read_verilog ../top.v
synth -top top
flowmap -debug top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_debug_relax.ys
read_verilog ../top.v
synth -top top
flowmap -debug-relax top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_ffs.ys
read_verilog ../top_ffs.v
synth -top top
flowmap top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_latch.ys
read_verilog ../top_latch.v
synth -top top
flowmap top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_maxlut.ys
read_verilog ../top.v
synth -top top
flowmap -maxlut 4 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_minlut.ys
read_verilog ../top.v
synth -top top
flowmap -minlut 2 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_optarea.ys
read_verilog ../top.v
synth -top top
flowmap -optarea 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_r_alpha.ys
read_verilog ../top.v
synth -top top
flowmap -r-alpha 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_r_beta.ys
read_verilog ../top.v
synth -top top
flowmap -r-beta 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_r_gamma.ys
read_verilog ../top.v
synth -top top
flowmap -r-gamma 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_relax.ys
read_verilog ../top.v
synth -top top
flowmap -relax top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_relax_debug.ys
read_verilog ../top.v
synth -top top
flowmap -relax -debug top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_relax_debug_relax.ys
read_verilog ../top.v
synth -top top
flowmap -relax -debug-relax top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_top.ys
read_verilog ../top.v
synth -top top
flowmap top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_command.ys
read_verilog ../top.v
proc
fsm
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_command_expand.ys
read_verilog ../top.v
proc
fsm -expand
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_command_export.ys
read_verilog ../top.v
proc
fsm -export
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encfile.ys
read_verilog ../top.v
proc
fsm -encfile fsm.fsm
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_auto.ys
......@@ -7,6 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding auto
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_binary.ys
read_verilog ../top.v
proc
fsm -encoding binary
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_none.ys
......@@ -7,6 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding none
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_one-hot.ys
read_verilog ../top.v
proc
fsm -encoding one-hot
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_unknown.ys
......@@ -7,6 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding unknown
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_user.ys
......@@ -7,6 +7,6 @@ fsm_map
fsm
fsm -encoding binary
fsm -encoding user
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_fm_set_fsm_file.ys
read_verilog ../top.v
proc
fsm -fm_set_fsm_file file.file
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_fullexpand.ys
read_verilog ../top.v
proc
fsm -fullexpand
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_nodetect.ys
read_verilog ../top.v
proc
fsm -nodetect
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_nomap.ys
read_verilog ../top.v
proc
fsm -nomap
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_norecode.ys
read_verilog ../top.v
proc
fsm -norecode
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_export/fsm_export_couldnt_open_file_fail.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_all_opt.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_cant_open_encfile_fail.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_cant_open_fm_set_fsm_file_fail.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encfile.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_binary.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_binary_twice.ys
......@@ -8,4 +8,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_isnt_supported_fail.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_one_hot.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_fm_set_fsm_file.ys
......@@ -7,4 +7,4 @@ opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy.ys
......@@ -6,4 +6,4 @@ opt
hierarchy
synth -top top
hierarchy
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_auto_top.ys
read_verilog ../top.v
hierarchy -auto-top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_check.ys
read_verilog ../top.v
hierarchy -check -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_chparam.ys
read_verilog ../top.v
hierarchy -chparam x 1 -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_chparam_overwr.ys
read_verilog ../top.v
hierarchy -chparam x 1 -chparam x 2 -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_generate.ys
read_verilog ../top.v
hierarchy -generate dff adff adffn i@1:i o@2:o io@3:io
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_huge.ys
......@@ -4,4 +4,4 @@ hierarchy -generate -check -simcheck -purge_lib -keep_positionals -keep_portwidt
design -reset
read_verilog ../top.v
synth
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_keep_portwidths.ys
read_verilog ../top.v
hierarchy -keep_portwidths -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_keep_positionals.ys
read_verilog ../top.v
hierarchy -keep_positionals -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_libdir.ys
read_verilog ../top.v
hierarchy -libdir libdir -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_module_not_found_fail.ys
read_verilog ../top.v
hierarchy -top uu
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_no_top_module_fail.ys
hierarchy -simcheck
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_nokeep_asserts.ys
read_verilog ../top.v
hierarchy -nokeep_asserts -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_purge_lib.ys
read_verilog ../top.v
hierarchy -purge_lib -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_simcheck.ys
read_verilog ../top.v
hierarchy -simcheck -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_top.ys
read_verilog ../top.v
hierarchy -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_top_requires_args_fail.ys
read_verilog ../top.v
hierarchy -top
synth -top top
write_verilog synth.v
simple_reviewed/ice40_dsp/ice40_dsp_mult_a_larger.ys
read_verilog ../top_mult_a_larger.v
proc
ice40_dsp
stat
select -assert-none t:SB_MAC16
synth_ice40 -top top
simple_reviewed/ice40_dsp/ice40_dsp_mult_b_larger.ys
read_verilog ../top_mult_b_larger.v
proc
ice40_dsp
stat
select -assert-none t:SB_MAC16
synth_ice40 -top top
simple_reviewed/ice40_dsp/ice40_dsp_mult_out_larger.ys
read_verilog ../top_mult_out_larger.v
proc
ice40_dsp
stat
select -assert-none t:SB_MAC16
synth_ice40 -top top
simple_reviewed/ice40_dsp/ice40_dsp_mult_signed.ys
read_verilog ../top_mult_signed.v
proc
ice40_dsp
stat
select -assert-count 1 t:SB_MAC16
synth_ice40 -top top
simple_reviewed/memory/memory.ys
read_verilog ../top.v
proc
memory
stat
simple_reviewed/memory/memory_bram_cant_open_rules_file_fail.ys
......@@ -5,4 +5,4 @@ memory_bram -rules uuu
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_bram_opt.ys
......@@ -5,4 +5,4 @@ memory -bram ../words.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_bram_syntax_error_in_rules_fail.ys
......@@ -5,4 +5,4 @@ memory_bram -rules ../rules.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_memx_opt.ys
......@@ -5,4 +5,4 @@ memory -memx
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_nomap.ys
......@@ -6,4 +6,4 @@ memory_map
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_nordff.ys
......@@ -19,4 +19,4 @@ memory_unpack
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_nordff_opt.ys
......@@ -5,4 +5,4 @@ memory -nordff
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_share.ys
......@@ -20,4 +20,4 @@ memory_share
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_single_port.ys
......@@ -5,4 +5,4 @@ memory
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/nlutmap/nlutmap_error_fail.ys
......@@ -2,5 +2,5 @@ read_verilog ../top.v
synth -top top
abc -lut 5
nlutmap -luts 6 -assert
tee -o result.log dump
write_verilog synth.v
dump
simple_reviewed/opt/opt.ys
......@@ -3,7 +3,6 @@ proc
fsm_detect
fsm_extract
opt
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
......
simple_reviewed/opt/opt_clkinv.ys
......@@ -3,7 +3,6 @@ proc
fsm_detect
fsm_extract
opt -clkinv
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
......
simple_reviewed/opt/opt_fast.ys
......@@ -3,8 +3,6 @@ proc
fsm_detect
fsm_extract
opt -fast
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 9 t:$mux
......
simple_reviewed/opt/opt_fine.ys
......@@ -4,7 +4,6 @@ fsm_detect
fsm_extract
opt -fine
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
......
simple_reviewed/opt/opt_full.ys
......@@ -4,7 +4,6 @@ fsm_detect
fsm_extract
opt -full
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 5 t:$mux
......
simple_reviewed/opt/opt_keepdc.ys
......@@ -3,7 +3,7 @@ proc
fsm_detect
fsm_extract
opt -keepdc
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
......
simple_reviewed/opt/opt_mux_bool.ys
......@@ -4,7 +4,6 @@ fsm_detect
fsm_extract
opt -mux_bool
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 5 t:$mux
......
simple_reviewed/opt/opt_mux_undef.ys
......@@ -4,7 +4,6 @@ fsm_detect
fsm_extract
opt -mux_undef
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 7 t:$mux
......
simple_reviewed/opt/opt_purge.ys
......@@ -3,7 +3,6 @@ proc
fsm_detect
fsm_extract
opt -purge
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
......
simple_reviewed/opt/opt_sat.ys
......@@ -4,7 +4,6 @@ fsm_detect
fsm_extract
opt -sat
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
......
simple_reviewed/opt/opt_share_all.ys
......@@ -3,7 +3,6 @@ proc
fsm_detect
fsm_extract
opt -share_all
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
......
simple_reviewed/opt/opt_undriven.ys
......@@ -3,8 +3,6 @@ proc
fsm_detect
fsm_extract
opt -undriven
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
......
simple_reviewed/opt_demorgan/opt_demorgan.ys
......@@ -2,4 +2,3 @@ read_verilog ../top.v
techmap -autoproc
extract_reduce
opt_demorgan top
stat
simple_reviewed/opt_demorgan/opt_demorgan_reduce.ys
......@@ -2,4 +2,3 @@ read_verilog ../top_reduce.v
techmap -autoproc
extract_reduce
opt_demorgan top
stat
simple_reviewed/opt_lut/opt_lut_dlogic.ys
......@@ -4,4 +4,4 @@ opt_lut -dlogic $_ANDNOT_:A=I0
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/opt_lut/opt_lut_limit.ys
......@@ -4,4 +4,4 @@ opt_lut -limit 2
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/opt_lut/opt_lut_limit_0.ys
......@@ -4,4 +4,4 @@ opt_lut -limit 0
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/opt_merge_reduce/opt_merge.ys
......@@ -13,4 +13,4 @@ opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
simple_reviewed/opt_merge_reduce/opt_merge_nomux.ys
......@@ -13,4 +13,4 @@ opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
simple_reviewed/opt_merge_reduce/opt_merge_share_all.ys
......@@ -13,4 +13,4 @@ opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
simple_reviewed/opt_merge_reduce/opt_merge_share_all_2.ys
......@@ -13,4 +13,4 @@ opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
simple_reviewed/opt_rmdff/dff.ys
......@@ -7,4 +7,4 @@ proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dff_async.ys
......@@ -8,4 +8,4 @@ proc
flatten
#opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dff_ff.ys
......@@ -8,4 +8,4 @@ proc
flatten
#opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dff_keepdc.ys
......@@ -4,4 +4,4 @@ proc
flatten
opt
opt_rmdff -keepdc
write_verilog synth.v
simple_reviewed/opt_rmdff/dff_sat.ys
......@@ -4,4 +4,4 @@ proc
flatten
opt
opt_rmdff -sat
write_verilog synth.v
simple_reviewed/opt_rmdff/dffc.ys
......@@ -4,4 +4,4 @@ proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dffcp.ys
......@@ -4,4 +4,4 @@ proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dffcp_d0.ys
......@@ -4,4 +4,4 @@ proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dffr.ys
......@@ -4,4 +4,4 @@ proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dffsr.ys
......@@ -4,4 +4,4 @@ proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/latsr.ys
......@@ -4,4 +4,4 @@ proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/prep/prep.ys
read_verilog ../top.v
prep
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_auto_top.ys
read_verilog ../top.v
prep -auto-top
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_error_fail.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
select dffe
prep
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_flatten.ys
read_verilog ../top.v
prep -flatten
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_ifx.ys
read_verilog ../top.v
prep -ifx
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_memx.ys
read_verilog ../top.v
prep -memx
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_nokeepdc.ys
read_verilog ../top.v
prep -nokeepdc
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_nomem.ys
read_verilog ../top.v
prep -nomem
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_nordff.ys
read_verilog ../top.v
prep -nordff
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_rdff.ys
read_verilog ../top.v
prep -rdff
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_run.ys
read_verilog ../top.v
prep -run begin:check
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_run_begin.ys
read_verilog ../top.v
prep -run begin
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_top.ys
read_verilog ../top.v
prep -top top
synth -top top
write_verilog synth.v
simple_reviewed/proc_arst/proc_arst.ys
read_verilog ../top.v
proc_arst
synth -top top
write_verilog synth.v
simple_reviewed/proc_arst/proc_arst_global_rst.ys
read_verilog ../top.v
proc_arst -global_arst top/rst
synth -top top
write_verilog synth.v
simple_reviewed/proc_arst/proc_arst_global_rst_a.ys
read_verilog ../top_reduce.v
proc_arst -global_arst a
synth -top top
write_verilog synth.v
simple_reviewed/share/share.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
share
synth -top top
write_verilog synth.v
simple_reviewed/share/share_aggressive.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
share -aggressive
synth -top top
write_verilog synth.v
simple_reviewed/share/share_aggressive_fsm.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_fsm.v
proc
share -aggressive
synth -top top
write_verilog synth.v
simple_reviewed/share/share_aggressive_macc.ys
......@@ -4,4 +4,4 @@ flatten
alumacc
share -aggressive
synth -top top
write_verilog synth.v
simple_reviewed/share/share_aggressive_shr.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_shr.v
proc
share -aggressive
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fast.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
share -fast
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fast_fsm.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_fsm.v
proc
share -fast
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fast_macc.ys
......@@ -4,4 +4,4 @@ flatten
alumacc
share -fast
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fast_shr.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_shr.v
proc
share -fast
synth -top top
write_verilog synth.v
simple_reviewed/share/share_force.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
share -force
synth -top top
write_verilog synth.v
simple_reviewed/share/share_force_fsm.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_fsm.v
proc
share -force
synth -top top
write_verilog synth.v
simple_reviewed/share/share_force_macc.ys
......@@ -4,4 +4,4 @@ proc
alumacc
share -force
synth -top top
write_verilog synth.v
simple_reviewed/share/share_force_shr.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_shr.v
proc
share -force
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fsm.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_fsm.v
proc
share
synth -top top
write_verilog synth.v
simple_reviewed/share/share_limit.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
share -limit 1
synth -top top
write_verilog synth.v
simple_reviewed/share/share_limit_fsm.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_fsm.v
proc
share -limit 1
synth -top top
write_verilog synth.v
simple_reviewed/share/share_limit_macc.ys
......@@ -4,4 +4,4 @@ flatten
alumacc
share -limit 1
synth -top top
write_verilog synth.v
simple_reviewed/share/share_limit_shr.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_shr.v
proc
share -limit 1
synth -top top
write_verilog synth.v
simple_reviewed/share/share_macc.ys
......@@ -3,4 +3,4 @@ proc
alumacc
share
synth -top top
write_verilog synth.v
simple_reviewed/share/share_shr.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_shr.v
proc
share
synth -top top
write_verilog synth.v
simple_reviewed/shregmap/shregmap_clkpol_any.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -clkpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_clkpol_neg.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -clkpol neg
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_clkpol_pos.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -clkpol pos
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_any.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -enpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_any_or_none.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -enpol any_or_none
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_neg.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -enpol neg
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_none.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -enpol none
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_pos.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -enpol pos
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_init.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -init
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_keep_after.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -keep_after 5
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_keep_before.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -keep_before 3
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_match.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -match \GP_DFF
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_match_clkpol_fail.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -match -clkpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_match_enpol_fail.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -match foobar -enpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_match_params_fail.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
shregmap -params -match 2:2
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_maxlen.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -maxlen 10
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_minlen.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -minlen 4
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_params.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -params
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_resetable.ys
......@@ -3,4 +3,4 @@ synth_greenpak4
shregmap
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_tech.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_zinit.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -zinit
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_zinit_init_fail.ys
......@@ -3,4 +3,4 @@ synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -zinit -init
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/simplemap.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
prep
simplemap
synth
write_verilog synth.v
simple_reviewed/shregmap/simplemap_slice_concat.ys
......@@ -3,4 +3,4 @@ synth
splice
simplemap top
synth
write_verilog synth.v
simple_reviewed/shregmap/simplemap_top.ys
......@@ -3,4 +3,4 @@ prep
dff2dffe
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
prep
simplemap
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_mem.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_mem_slice_concat.v
prep
simplemap
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_reduce.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_reduce.v
prep
simplemap
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_splice_concat.ys
......@@ -3,4 +3,4 @@ synth
splice
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_splice_concat_mem.ys
......@@ -3,4 +3,4 @@ synth
splice
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_splice_reduce.ys
......@@ -3,4 +3,4 @@ synth
splice
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_top.ys
......@@ -3,4 +3,4 @@ prep
dff2dffe
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_top_mem.ys
......@@ -3,4 +3,4 @@ prep
dff2dffe
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_top_reduce.ys
......@@ -2,4 +2,4 @@ read_verilog ../top_reduce.v
prep
simplemap top
synth
write_verilog synth.v
simple_reviewed/submod/submod.ys
......@@ -3,4 +3,4 @@ proc
hierarchy
submod
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_copy.ys
......@@ -3,4 +3,4 @@ proc
hierarchy
submod -copy
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_error_fail.ys
......@@ -3,4 +3,4 @@ proc
hierarchy
submod -name fsm -name fsm2
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_mem.ys
......@@ -5,4 +5,4 @@ submod
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_name.ys
......@@ -3,4 +3,4 @@ proc
hierarchy
submod -copy -name a top
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_no_hier.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
submod
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_no_proc.ys
read_verilog ../top.v
submod
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_top.ys
......@@ -3,4 +3,4 @@ proc
hierarchy
submod -copy top
synth -top top
write_verilog synth.v
simple_reviewed/synth/synth.ys
read_verilog ../top.v
synth
write_verilog synth.v
simple_reviewed/synth/synth_abc9.ys
read_verilog ../top.v
synth -abc9 -lut 5
write_verilog synth.v
simple_reviewed/synth/synth_abc9_no_lut_fail.ys
read_verilog ../top.v
synth -abc9
write_verilog synth.v
simple_reviewed/synth/synth_auto_top.ys
read_verilog ../top.v
synth -auto-top
write_verilog synth.v
simple_reviewed/synth/synth_encfile.ys
read_verilog ../top.v
synth -encfile enc.file
write_verilog synth.v
simple_reviewed/synth/synth_error_fail.ys
read_verilog ../top.v
select adff
synth
write_verilog synth.v
simple_reviewed/synth/synth_flatten.ys
read_verilog ../top.v
synth -flatten
write_verilog synth.v
simple_reviewed/synth/synth_lut.ys
read_verilog ../top.v
synth -lut 5
write_verilog synth.v
simple_reviewed/synth/synth_noabc.ys
read_verilog ../top.v
synth -noabc
write_verilog synth.v
simple_reviewed/synth/synth_noabc_lut.ys
read_verilog ../top.v
synth -noabc -lut 3
write_verilog synth.v
simple_reviewed/synth/synth_noalumacc.ys
read_verilog ../top.v
synth -noalumacc
write_verilog synth.v
simple_reviewed/synth/synth_nofsm.ys
read_verilog ../top.v
synth -nofsm
write_verilog synth.v
simple_reviewed/synth/synth_nordff.ys
read_verilog ../top.v
synth -nordff
write_verilog synth.v
simple_reviewed/synth/synth_noshare.ys
read_verilog ../top.v
synth -noshare
write_verilog synth.v
simple_reviewed/synth/synth_run.ys
read_verilog ../top.v
synth -run begin
write_verilog synth.v
simple_reviewed/synth/synth_run_full.ys
read_verilog ../top.v
synth -run begin:check
write_verilog synth.v
simple_reviewed/synth/synth_top.ys
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/techmap/techmap.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
techmap
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_assert.ys
......@@ -3,4 +3,4 @@ proc
dff2dffe
techmap -assert -map +/techmap.v +/simlib.v
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_autoproc.ys
read_verilog ../top.v
techmap -autoproc
write_verilog synth.v
simple_reviewed/techmap/techmap_d.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
techmap -D U
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_extern.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
techmap -extern
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_i.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
techmap -I techmap
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_map.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
techmap -map +/techmap.v
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_max_iter.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
techmap -max_iter 2
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_recursive.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
techmap -recursive
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_wb.ys
read_verilog ../top.v
techmap -wb
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_eqpmux.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -eqpmux
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
test_pmgen -eqpmux
simple_reviewed/test_pmgen/test_pmgen_generate_eqpmux.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate eqpmux
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
test_pmgen -generate eqpmux
simple_reviewed/test_pmgen/test_pmgen_generate_ice40_dsp.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate ice40_dsp
test_pmgen -generate ice40_dsp
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_peepopt_muldiv.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate peepopt-muldiv
test_pmgen -generate peepopt-muldiv
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_peepopt_shiftmul.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate peepopt-shiftmul
test_pmgen -generate peepopt-shiftmul
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_reduce.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate reduce
test_pmgen -generate reduce
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_xilinx_srl_fixed.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate xilinx_srl.fixed
test_pmgen -generate xilinx_srl.fixed
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_xilinx_srl_variable.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate xilinx_srl.variable
test_pmgen -generate xilinx_srl.variable
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_reduce_chain.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -reduce_chain
test_pmgen -reduce_chain
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_reduce_tree.ys
read_verilog ../top.v
proc
tee -o result.log test_pmgen -reduce_tree
test_pmgen -reduce_tree
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/tribuf/tribuf_top.ys
......@@ -3,4 +3,4 @@ proc
tribuf tristate
select -assert-count 1 t:$tribuf
synth -top top
write_verilog synth.v
simple_reviewed/tristate/tristate.ys
read_verilog ../top.v
synth -top top
stat
simple_reviewed/tristate/tristate_case.ys
read_verilog ../top_case.v
synth -top top
stat
simple_reviewed/tristate/tristate_const_0.ys
read_verilog ../top_const_0.v
synth -top top
stat
simple_reviewed/tristate/tristate_const_1.ys
read_verilog ../top_const_1.v
synth -top top
stat
simple_reviewed/tristate/tristate_const_data.ys
read_verilog ../top_const_data.v
synth -top top
stat
simple_reviewed/tristate/tristate_if.ys
read_verilog ../top_if.v
synth -top top
stat
simple_reviewed/tristate/tristate_proc_asmt.ys
read_verilog ../top_proc_asmt.v
synth -top top
stat
simple_reviewed/zinit/zinit.ys
read_verilog ../top.v
synth -top top
zinit
tee -o result.log dump
write_verilog synth.v
dump
simple_reviewed/zinit/zinit_failed_to_handle_fail.ys
read_verilog ../synth.v
zinit
tee -o result.log dump
write_verilog synth.v
dump
simple_reviewed/zinit/zinit_singleton.ys
read_verilog ../top.v
synth -top top
zinit -all
tee -o result.log dump
write_verilog synth.v
dump
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