Rewrite failing tests to be less brittle

architecture/synth_ice40/synth_ice40_nobram.ys

@@ -5,13 +5,6 @@ hierarchy -top top
 proc
 memory -nomap
 equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-
-#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
-
 design -load postopt
 cd top
 select -assert-count 1 t:SB_RAM40_4K
@@ -22,16 +15,7 @@ hierarchy -top top
 proc
 memory -nomap
 equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -nobram
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-
-#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
 design -load postopt
 cd top
-stat
-select -assert-count 6 t:SB_DFF
-select -assert-count 384 t:SB_DFFE
-select -assert-count 373 t:SB_LUT4
-select -assert-none t:SB_DFF t:SB_DFFE t:SB_LUT4 %% t:* %D
+select -assert-none t:SB_RAM40_4K
+select -assert-none t:SB_DFF* t:SB_LUT4 %% t:* %D

simple/iopadmap/iopadmap.pat

-cell \\IOBUF $auto$iopadmap.cc

simple/iopadmap/iopadmap.ys

 read_verilog ../top.v
 proc
-tee -o result1.out dump
 iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad OBUF I:O -inoutpad IOBUFE O:IO -toutpad OBUFT OE:I:O -tinoutpad IOBUF OE:O:I:IO
 iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad OBUF I:O -inoutpad IOBUFE O:IO -toutpad OBUFT OE:I:O -tinoutpad IOBUF OE:O:I:IO
-tee -o result.out dump
+select -assert-any t:IOBUF

simple/iopadmap/iopadmap_dont_map.pat

-cell \\IBUF $auto$iopadmap.cc

simple/iopadmap/iopadmap_dont_map.ys

 read_verilog ../top.v
 proc
-tee -o result1.out dump
 iopadmap -widthparam wp
 iopadmap -nameparam np
 iopadmap -bits
@@ -9,4 +8,4 @@ iopadmap -outpad OBUF I:O
 iopadmap -inoutpad IOBUFE O:IO
 iopadmap -toutpad OBUFT OE:I:O
 iopadmap -tinoutpad IOBUF OE:O:I:IO
-tee -o result.out dump
+select -assert-any t:IBUF