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yosys-tests
Commit 7a0d0c6d by Miodrag Milanovic
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Added properly handled regression tests

parent c7e05d2b
Showing with 185 additions and 386 deletions
generate-new.py 0 → 100644
import os
is_heavy_enabled = int(os.getenv('ENABLE_HEAVY_TESTS', '0')) == 1
for root, dirs, files in sorted(os.walk(".")):
for file in files:
if file.endswith('.ys') or file.endswith('run-test.sh'):
dir = os.path.basename(root)
work = os.path.splitext(file)[0]
heavy = os.path.exists(os.path.join(dir, "heavy_test"))
is_disabled = os.path.exists(os.path.join(dir, work + ".disable"))
print("all: {0}/work_{1}/.stamp\n"
"{0}/work_{1}/.stamp:".format(dir, work))
if (is_disabled):
print("\t@echo 'Skipping disabled test {0}..'".format(dir, work))
continue
if (heavy and not is_heavy_enabled):
print("\t@echo 'Skipping heavy test {0}..'".format(dir, work))
continue
print("\t@echo 'Running {2}{1}..'\n"
"\t@../run-new.sh {0} {1}\n"
"clean::\n"
"\t@echo 'Cleaning {1}..'\n"
"\t@rm -rf {0}/work_{1}".format(dir, work, "heavy " if heavy else ""))
print(".PHONY: all clean")
\ No newline at end of file
regression/Makefile
PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
all:
all: run-test.mk
run-test.mk: ../generate.py
@$(PYTHON_EXECUTABLE) ../generate.py > run-test.mk
run-test.mk: ../generate-new.py
@$(PYTHON_EXECUTABLE) ../generate-new.py > run-test.mk
include run-test.mk
clean::
@rm -rf run-test.mk
@echo 'Cleaning run-test.mk..'
.PHONY: all clean
regression/common.v deleted 100644 → 0
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#2
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_X(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
regression/issue_00018/issue_00018.ys
read_verilog ../top.v
read_verilog top.v
synth -top d
regression/issue_00041/issue_00041.ys
read_verilog ../top.v
read_verilog top.v
synth -top top
write_verilog synth.v
regression/issue_00059/issue_00059.ys
read_verilog ../top.v
read_verilog top.v
#Myname: added some comment with a colon
synth -top top
regression/issue_00065/issue_00065.ys
read_verilog ../top.v
read_verilog top.v
synth -top top
regression/issue_00067/issue_00067.ys
read_verilog ../top.v
read_verilog top.v
freduce
regression/issue_00071/issue_00071.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00078/top.v → regression/issue_00078/is28.v
/* Generated by Yosys 0.5+284 (git sha1 f40d1b7, gcc 5.2.1-15 -fPIC -Os) */
(* src = "test.v:1" *)
module top(X, Y);
module is28(X, Y);
wire _0000_;
wire _0001_;
wire _0002_;
......
regression/issue_00078/issue_00078.pat deleted 100644 → 0
\\\X\[0\] , \\\X\[1\] , \\\X\[2\] ,
regression/issue_00078/issue_00078.ys
read_verilog ../top.v
read_verilog is28.v
hierarchy
splitnets -ports
write_verilog result.out
!mkdir -p work_issue_00078
write_verilog work_issue_00078/synth.v
!grep "(\\\X\[0\] , \\\X\[1\] , \\\X\[2\] ," work_issue_00078/synth.v > /dev/null
\ No newline at end of file
regression/issue_00081/issue_00081.ys
logger -expect error "syntax error" 1
read_verilog ../top.v
read_verilog top.v
regression/issue_00082/issue_00082.ys 0 → 100644
logger -expect error "no AST_WIRE node" 1
read_verilog top.v
regression/issue_00083/issue_00083_fail.ys
read_verilog ../top.v
logger -expect warning "Deep recursion in AST simplifier." 1
read_verilog top.v
regression/issue_00084/issue_00084.ys
read_verilog ../top.v
read_verilog top.v
synth_xilinx -top top
cd top
select -assert-count 1 t:RAMB18E1
\ No newline at end of file
regression/issue_00085/issue_00085.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00086/issue_00086.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00088/issue_00088.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00089/issue_00089.ys 0 → 100644
logger -expect error "syntax error, unexpected \$undefined" 1
read_verilog top.v
regression/issue_00091/issue_00091.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00093/issue_00093.ys 0 → 100644
logger -expect error "syntax error, unexpected '\+'" 1
read_verilog top.v
regression/issue_00093/issue_00093_fail.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
regression/issue_00095/issue_00095.ys 0 → 100644
logger -expect error "syntax error, unexpected '#'" 1
read_verilog top.v
regression/issue_00095/issue_00095_fail.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
regression/issue_00096/issue_00096.ys 0 → 100644
logger -expect error "syntax error, unexpected TOK_INOUT" 1
read_verilog top.v
regression/issue_00096/issue_00096_fail.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
regression/issue_00098/issue_00098.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00099/issue_00099.ys 0 → 100644
logger -expect error "syntax error, unexpected ','" 1
read_verilog top.v
regression/issue_00102/issue_00102.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00111/issue_00111.ys
read_verilog ../top.v
read_verilog top.v
synth -top top
splitnets -ports
hierarchy -check
regression/issue_00114/issue_00114.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00126/issue_00126.ys
read_verilog ../top.v
read_verilog top.v
hierarchy -top test
write_verilog -noexpr -norename result.out
logger -expect warning "Module test contains unmapped RTLIL processes" 1
write_verilog -noexpr -norename
regression/issue_00128/issue_00128.ys
read_verilog ../top.v
read_verilog top.v
synth -top top
regression/issue_00132/issue_00132.ys
read_verilog -defer ../top.v
chparam -set incr 42 topmod
read_verilog -defer top.v
chparam -set incr 42 top
prep -flatten
sat -verify -prove-asserts -show-ports -set a[7:0] 1 -prove y[7:0] 43
regression/issue_00133/issue_00133.ys
read_verilog ../top.v
synth -top top
read_verilog top.v
prep -flatten
sat -verify -prove-asserts -show-ports -prove y a
regression/issue_00134/issue_00134.ys
read_verilog ../top.v
read_verilog top.v
hierarchy -top task_bug
proc; opt; memory; dff2dffe; wreduce; clean; opt
write_verilog -noexpr -norename result.out
proc
sat -verify -prove-asserts -show-ports -prove do in_data
regression/issue_00160/issue_00160.ys
read_verilog ../top.v
read_verilog top.v
#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
......
regression/issue_00171/issue_00171.ys
read_verilog ../top.v
read_verilog top.v
proc; opt; fsm; opt; memory; opt; techmap; opt
scc -all_cell_types
#and then put each found SCC into a module using submod.
......
regression/issue_00173/issue_00173.ys
read_verilog ../top.v
read_verilog top.v
proc
sat -verify -prove-asserts -show-ports -prove co bi
#TODO: check if we should take care of order or not
\ No newline at end of file
regression/issue_00174/issue_00174.ys
read_verilog ../top.v
read_verilog top.v
hierarchy -top top
write_verilog -noattr t1.v
proc
opt -full
techmap
......
regression/issue_00175/issue_00175.ys
read_verilog ../top.v
read_verilog top.v
hierarchy
proc
opt
......
regression/issue_00182/issue_00182.ys
read_verilog ../top.v
synth_ice40 -blif litescope.bli -top top
read_verilog top.v
synth_ice40 -top top
regression/issue_00183/issue_00183.ys
read_verilog ../top.v
synth_ice40 -top top -blif test.blif
read_verilog top.v
synth_ice40 -top top
regression/issue_00186/issue_00186.pat deleted 100644 → 0
assign _07_\[0\] = adr\[0\] ? \\ram\[3\] \[0\] : \\ram\[2\] \[0\];
assign _07_\[1\] = adr\[0\] ? \\ram\[3\] \[1\] : \\ram\[2\] \[1\];
regression/issue_00186/issue_00186.ys
read_verilog -DTEST_1 ../top.v
read_verilog -DTEST_1 top.v
hierarchy -top top
proc; memory
opt -full
techmap
write_verilog -noattr result.out
synth
rename -top gold
design -save gold
design -reset
read_verilog -DTEST_2 top.v
hierarchy -top top
proc; memory
opt -full
synth
rename -top gate
design -copy-from gold gold
equiv_make gold gate equiv
equiv_induct
equiv_status -assert equiv
\ No newline at end of file
regression/issue_00194/issue_00194.ys
read_verilog ../top.v
read_verilog top.v
proc
prep -flatten
sat -verify -prove-asserts -show-ports -prove y a
regression/issue_00195/issue_00195.ys
read_verilog ../top.v
read_verilog top.v
synth -top top
write_verilog synth.v
sat -verify -prove-asserts -show-ports -prove b 123456
regression/issue_00195/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00195/top.v
module top(b);
input b;
module top(output [17:0] b);
wire a = 100_000.0;
assign b = 123_456.0;
endmodule
regression/issue_00196/issue_00196.ys 0 → 100644
logger -expect error "Found posedge/negedge event on a signal that is not 1 bit wide!" 1
read_verilog top.v
regression/issue_00196/issue_00196_fail.pat deleted 100644 → 0
ERROR: Found posedge/negedge event on a signal that is not 1 bit wide!
regression/issue_00196/issue_00196_fail.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -json 3pdrive.json
regression/issue_00210/issue_00210.ys
read_verilog ../top.v
read_verilog top.v
sat -verify -prove-asserts -show-ports -set-any-undef 0 -prove result 2
regression/issue_00282/issue_00282.ys
read_verilog ../top.v
read_verilog top.v
synth -top top
#synth_ice40 -top top
# Next will fail if synth_ice40 is executed
select -assert-count 1 t:$_DFF_P_
regression/issue_00283/issue_00283.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00283/top.v
module top
#(parameter WIDTH = 64, C_WIDTH = 8, DE = 4)
(
input clk,
input reset,
input [C_WIDTH*WIDTH-1:0] c_data_in_port,
input [DE*C_WIDTH -1:0] d_one_hot,
input [C_WIDTH -1:0] c_data_in_en,
module top(input clk, enable, output reg y);
output reg [DE*WIDTH-1:0] d_data_out_port,
output reg [DE-1:0] d_data_out_en
);
wire [1:0] foo [1:0];
integer i;
reg [ WIDTH-1:0] clients_data_in [ C_WIDTH-1:0];
reg [ C_WIDTH-1:0] devices_one_hot_client_sel [ DE-1:0];
reg [ WIDTH-1:0] devices_data_out [ DE-1:0];
reg [ WIDTH-1:0] clients_data_in_s [ C_WIDTH-1:0];
reg [ C_WIDTH-1:0] devices_one_hot_client_sel_s [ DE-1:0];
wire [ WIDTH-1:0] devices_data_out_p [ DE-1:0];
wire [ C_WIDTH-1:0] clients_data_rotate [ WIDTH-1:0];
wire [ DE-1:0] devices_data_rotate [ WIDTH-1:0];
reg [ DE-1:0] clients_one_hot_device_sel [ C_WIDTH-1:0];
wire [ DE-1:0] dev_en;
wire [ DE-1:0] data_out_en;
integer client, device;
always @*
begin
for(client = 0; client < C_WIDTH; client = client + 1) begin
clients_data_in[client] = c_data_in_port[client*WIDTH+:WIDTH];
end
end
always @*
begin
for(client = 0; client < C_WIDTH; client = client + 1) begin
clients_one_hot_device_sel[client] = d_one_hot[client*DE+:DE];
end
end
always @*
begin
for (device = 0; device < DE; device = device + 1) begin
for(client = 0; client < C_WIDTH; client = client + 1) begin
devices_one_hot_client_sel[device][client] = clients_one_hot_device_sel[client][device];
end
end
end
genvar k;
integer rowsel;
genvar i, j, nw;
always @(posedge clk or negedge reset)
if (!reset)
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
devices_data_out[rowsel][WIDTH-1:1] <= 'b0;
else begin
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
if (dev_en[rowsel]==1'b1)
devices_data_out[rowsel][WIDTH-1:1] <= devices_data_out_p[rowsel][WIDTH-1:1];
end
always @(posedge clk or negedge reset)
if (!reset)
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
devices_data_out[rowsel][0] <= 1'b0;
else
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
devices_data_out[rowsel][0] <= devices_data_out_p[rowsel][0];
always @*
begin
for(rowsel = 0; rowsel < C_WIDTH; rowsel=rowsel+1) begin
clients_data_in_s[rowsel][WIDTH-1:0] = clients_data_in[rowsel];
end
end
always @*
begin
for(rowsel = 0; rowsel < DE; rowsel=rowsel+1) begin
devices_one_hot_client_sel_s[rowsel][C_WIDTH-1:0] = devices_one_hot_client_sel[rowsel][C_WIDTH-1:0];
end
end
generate
for (i = 0; i < DE; i=i+1) begin:gen_i3
assign dev_en[i] = |devices_one_hot_client_sel_s[i][C_WIDTH-1:0];
end
endgenerate
generate
for (i = 0; i < DE; i=i+1) begin:gen_i4
assign data_out_en[i] = |devices_one_hot_client_sel[i][C_WIDTH-1:0];
end
endgenerate
always @(posedge clk or negedge reset)
if (!reset)
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
d_data_out_en[rowsel] <= 1'b0;
else
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
d_data_out_en[rowsel] <= data_out_en[rowsel];
generate
for (i = 0; i < C_WIDTH; i=i+1) begin:gen_i
for (j = 0; j < WIDTH; j=j+1) begin:gen_j
assign clients_data_rotate[j][i] = clients_data_in_s[i][j];
end
end
endgenerate
generate
for (nw = 0; nw < WIDTH; nw=nw+1) begin : gen_nw
for (i = 0; i < DE; i=i+1) begin:gen_label
assign devices_data_rotate[nw][i] = |(clients_data_rotate[nw] & devices_one_hot_client_sel_s[i]);
end
end
endgenerate
generate
for (i = 0; i < WIDTH; i=i+1) begin:gen_i2
for (j = 0; j < DE; j=j+1) begin:gen_j2
assign devices_data_out_p[j][i] = devices_data_rotate[i][j];
end
end
endgenerate
always @*
begin
for (device = 0; device < DE; device = device + 1) begin
d_data_out_port[device*WIDTH+:WIDTH] = devices_data_out[device];
end
end
always @(posedge clk)
if (enable)
for (i = 0; i < 2; i=i+1)
y <= foo[0][0];
endmodule
regression/issue_00287/issue_00287.ys
tee -o result.out read_verilog -sv ../top.v
logger -werror "is implicitly declared at"
read_verilog -sv top.v
regression/issue_00289/issue_00289.ys
read_verilog -sv ../top.v
read_verilog -sv top.v
regression/issue_00291/issue_00291.ys
read_verilog -sv ../top.v
read_verilog -sv top.v
synth -top top
regression/issue_00300/issue_00300.ys
read_verilog ../top.v
read_verilog top.v
proc
opt
......@@ -7,9 +7,9 @@ dump
write_ilang foo.ilang
memory_collect
stat
#dump t:$mem
design -reset
read_ilang foo.ilang
stat
memory_collect
tee -o result.out dump t:$mem
select -assert-count 1 r:OFFSET=0
!rm foo.ilang
\ No newline at end of file
regression/issue_00306/issue_00306.ys
read_verilog ../top.v
proc
opt -full
read_verilog top.v
synth
regression/issue_00314/issue_00314.ys
read_verilog ../top.v
read_verilog top.v
synth -top top
regression/issue_00317/issue_00317.ys
read_verilog ../top.v
read_verilog top.v
regression/issue_00341/issue_00341.ys
read_verilog ../top.v
read_verilog top.v
equiv_make gold top_w equiv
hierarchy -top equiv
opt -purge
......
regression/issue_00342/issue_00342.ys
read_verilog -sv ../top.v
read_verilog -sv top.v
regression/issue_00349/issue_00349.ys
read_verilog -sv ../top.v
read_verilog -sv top.v
regression/issue_00350/issue_00350.ys
read_verilog -sv ../top.v
read_verilog top.v
synth
abc -dff -g AND
opt
write_aiger -ascii -symbols <file.out>
design -reset
read_aiger <file.out>
write_verilog result.out
abc -clk clk -g AND
opt_clean
select -assert-count 2 a:init
regression/issue_00350/top.v
module test
( input clk
, input in
, output out
);
reg [1:0] state = 0;
always @(posedge clk)
case (state)
0:
if (!in || in)
state <= 1;
else
state <= state;
1:
if (in)
state <= 1;
else
if (!in)
state <= 1;
else
state <= state;
endcase
always @(*)
case (state)
0:
out = 0;
1:
begin
if (in)
out = 1;
if (!in)
out = 0;
end
endcase
endmodule
module demo (input clk, input i, output o);
reg q = 0;
always @(posedge clk) q <= 1;
assign o = q & i;
endmodule
\ No newline at end of file
regression/issue_00361/issue_00361.ys
read_verilog -sv ../top.v
read_verilog -sv top.v
prep
alumacc
select -assert-count 63 t:$add
select -assert-count 2 t:$macc
select -assert-count 65 t:$mul
regression/issue_00362/issue_00362.ys 0 → 100644
read_verilog -sv top.v
logger -expect error "Output port top.inst.b \(inst\) is connected to constants: 1'1" 1
synth -top top
regression/issue_00362/issue_00362_fail.pat deleted 100644 → 0
ERROR: Output port top.inst.b (inst) is connected to constants: 1'1
regression/issue_00362/issue_00362_fail.ys deleted 100644 → 0
read_verilog -sv ../top.v
synth -top top
regression/issue_00372/issue_00372.ys
read_verilog -sv ../top.v
read_verilog -sv top.v
synth -top top
select -assert-count 1 t:$_DFF_P_
regression/issue_00432/issue_00432.ys
read_verilog -sv ../top.v
read_verilog -sv top.v
write_verilog result.v
select -assert-count 1 t:$shiftx
design -reset
read_verilog result.v
hierarchy -check
select -assert-count 1 t:$shiftx
!rm result.v
\ No newline at end of file
regression/issue_00444/issue_00444.ys
read_verilog -formal ../top.v
read_verilog -formal top.v
prep -top top
regression/issue_00449/issue_00449.ys
read_verilog -formal ../top.v
read_verilog -formal top.v
synth -top top
regression/issue_00457/issue_00457.ys
read_verilog -formal ../top.v
read_verilog -formal top.v
synth -top top
regression/issue_00481/issue_00481.ys
read_verilog ../top.v
synth_ice40 -blif tlt.blif
read_verilog top.v
synth_ice40
regression/issue_00502/issue_00502.ys
read_verilog ../top.v
read_verilog top.v
select -assert-any n:\\SUM/N10
regression/issue_00524/issue_00524.ys
read_verilog ../top.v
read_verilog top.v
synth_greenpak4 -part SLG46621V
select -assert-count 1 t:GP_INV
regression/issue_00527/issue_00527.ys
......@@ -3,7 +3,7 @@
#yosys -import
#set libfile osu018_stdcells_edit.lib
read_verilog -sv ../sd_rrmux.v
read_verilog -sv sd_rrmux.v
# Vanilla synth flow
hierarchy
......@@ -13,9 +13,9 @@ opt
techmap
opt
dfflibmap -liberty ../osu018_stdcells_edit.lib
dfflibmap -liberty osu018_stdcells_edit.lib
abc -liberty ../osu018_stdcells_edit.lib
abc -liberty osu018_stdcells_edit.lib
clean
......
regression/issue_00567/issue_00567.ys
read_verilog ../top.v
read_verilog top.v
synth_ice40 -nocarry
opt_clean
write_blif -attr -cname -param lut.eblif
select -assert-count 1 t:SB_LUT4
regression/issue_00582/issue_00582.ys 0 → 100644
logger -expect error "Failed to detect width for identifier \\valid!" 1
read_verilog top.v
synth_ice40 -top main
regression/issue_00582/issue_00582_fail.pat deleted 100644 → 0
ERROR: Failed to detect width for identifier \\valid!
run-new.sh 0 → 100755
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