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yosys-tests
Commit ea6ece16 by SergeyDegtyar
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Additional tests for 'backends' group.

parent 78573f91
Showing with 901 additions and 28 deletions
backends_reviewed/common/add_sub.v 0 → 100644
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
endmodule
backends_reviewed/common/adffs.v 0 → 100644
module top( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
backends_reviewed/common/counter.v 0 → 100644
module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset)
out <= 8'b0;
else
out <= out + 1;
endmodule
backends_reviewed/common/dffs.v 0 → 100644
module top ( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
backends_reviewed/common/latches.v 0 → 100644
module top ( input d, clk, en, output reg q );
always @*
if ( en )
q <= d;
endmodule
backends_reviewed/common/logic.v 0 → 100644
module top
(
input [0:7] in,
output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
);
assign B1 = in[0] & in[1];
assign B2 = in[0] | in[1];
assign B3 = in[0] ~& in[1];
assign B4 = in[0] ~| in[1];
assign B5 = in[0] ^ in[1];
assign B6 = in[0] ~^ in[1];
assign B7 = ~in[0];
assign B8 = in[0];
assign B9 = in[0:1] && in [2:3];
assign B10 = in[0:1] || in [2:3];
endmodule
backends_reviewed/write_blif/top_mem.v → backends_reviewed/common/memory.v
module top module top
( (
input [7:0] data_a, data_b, input [7:0] data_a,
input [6:1] addr_a, addr_b, input [6:1] addr_a,
input we_a, we_b, re_a, re_b, clk, input we_a, clk,
output reg [7:0] q_a, q_b output reg [7:0] q_a
); );
// Declare the RAM variable // Declare the RAM variable
reg [7:0] ram[63:0]; reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A // Port A
always @ (posedge clk) always @ (posedge clk)
begin begin
...@@ -21,24 +16,6 @@ module top ...@@ -21,24 +16,6 @@ module top
ram[addr_a] <= data_a; ram[addr_a] <= data_a;
q_a <= data_a; q_a <= data_a;
end end
if (re_b) q_a <= ram[addr_a];
begin
q_a <= ram[addr_a];
end
end end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule endmodule
backends_reviewed/common/mul.v 0 → 100644
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule
backends_reviewed/common/mux.v 0 → 100644
module top ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
backends_reviewed/common/shifter.v 0 → 100644
module top(out, clk, in);
output [7:0] out;
input signed clk, in;
reg signed [7:0] out = 0;
always @(posedge clk)
begin
out <= out >> 1;
out[7] <= in;
end
endmodule
backends_reviewed/common/tribuf.v 0 → 100644
module top(en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
backends_reviewed/write_aiger/write_aiger__add_sub.pat 0 → 100644
aig 72 8 0 8 64
22
38
58
78
85
104
124
144
backends_reviewed/write_aiger/write_aiger__add_sub.ys 0 → 100644
read_verilog -sv ../../common/add_sub.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__adffs.ys 0 → 100644
read_verilog -sv ../../common/adffs.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__counter.ys 0 → 100644
read_verilog -sv ../../common/counter.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__dffs.ys 0 → 100644
read_verilog -sv ../../common/dffs.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__latches.ys 0 → 100644
read_verilog -sv ../../common/latches.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__logic.pat 0 → 100644
aig 24 8 0 10 16
18
21
23
24
30
37
17
16
42
49
backends_reviewed/write_aiger/write_aiger__logic.ys 0 → 100644
read_verilog -sv ../../common/logic.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__mux.ys 0 → 100644
read_verilog -sv ../../common/mux.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__tribuf.ys 0 → 100644
read_verilog -sv ../../common/tribuf.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_btor/write_btor__add_sub.pat 0 → 100644
4 sub 1 3 2
5 output 4 B
6 add 1 3 2
7 output 6 A
backends_reviewed/write_btor/write_btor__add_sub.ys 0 → 100644
read_verilog -sv ../../common/add_sub.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__dffs.pat 0 → 100644
1 sort bitvec 1
2 input 1 clk
3 input 1 d
4 state 1
5 output 4 q
6 next 1 4 3
backends_reviewed/write_btor/write_btor__dffs.ys 0 → 100644
read_verilog -sv ../../common/dffs.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__logic.pat 0 → 100644
13 and 3 11 12
14 output 13 B9
15 slice 3 2 7 7
16 output 15 B8
17 not 3 15
18 output 17 B7
19 slice 3 2 6 6
20 xnor 3 15 19
21 output 20 B6
22 xor 3 15 19
23 output 22 B5
24 or 3 15 19
25 not 3 24
26 output 25 B4
27 and 3 15 19
28 not 3 27
29 output 28 B3
30 or 3 15 19
31 output 30 B2
32 and 3 15 19
33 output 32 B1
backends_reviewed/write_btor/write_btor__logic.ys 0 → 100644
read_verilog -sv ../../common/logic.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__mul.ys 0 → 100644
read_verilog -sv ../../common/mul.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__shifter.ys 0 → 100644
read_verilog -sv ../../common/shifter.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__tribuf.ys 0 → 100644
read_verilog -sv ../../common/tribuf.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_edif/write_edif__add_sub.pat 0 → 100644
(cell (rename id00001 "$add")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 4) (direction INPUT))
(port (array B 4) (direction INPUT))
(port (array Y 4) (direction OUTPUT))
)
)
)
(cell (rename id00002 "$sub")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 4) (direction INPUT))
(port (array B 4) (direction INPUT))
(port (array Y 4) (direction OUTPUT))
)
)
)
backends_reviewed/write_edif/write_edif__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__adffs.pat 0 → 100644
(cell (rename id00001 "$adff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port ARST (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__counter.pat 0 → 100644
(cell (rename id00001 "$add")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 8) (direction INPUT))
(port (array B 32) (direction INPUT))
(port (array Y 32) (direction OUTPUT))
)
)
)
(cell (rename id00002 "$adff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port ARST (direction INPUT))
(port (array Q 8) (direction OUTPUT))
(port (array D 8) (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__counter.ys 0 → 100644
read_verilog ../../common/counter.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__dffs.pat 0 → 100644
(cell (rename id00001 "$dff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__latches.pat 0 → 100644
(cell (rename id00005 "$dlatch")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port EN (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__logic.pat 0 → 100644
(cell (rename id00001 "$not")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00002 "$and")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00003 "$or")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00004 "$xor")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00005 "$xnor")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00006 "$logic_and")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 2) (direction INPUT))
(port (array B 2) (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00007 "$logic_or")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 2) (direction INPUT))
(port (array B 2) (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
backends_reviewed/write_edif/write_edif__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__mul.pat 0 → 100644
(cell (rename id00001 "$mul")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 6) (direction INPUT))
(port (array B 6) (direction INPUT))
(port (array Y 12) (direction OUTPUT))
)
)
)
backends_reviewed/write_edif/write_edif__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__mux.pat 0 → 100644
(cell (rename id00001 "$eq")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 3) (direction INPUT))
(port (array B 3) (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00002 "$pmux")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port (array B 8) (direction INPUT))
(port Y (direction OUTPUT))
(port (array S 8) (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__shifter.pat 0 → 100644
(cell (rename id00001 "$shr")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 8) (direction INPUT))
(port (array B 32) (direction INPUT))
(port (array Y 8) (direction OUTPUT))
)
)
)
(cell (rename id00002 "$dff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port (array Q 8) (direction OUTPUT))
(port (array D 8) (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__shifter.ys 0 → 100644
read_verilog ../../common/shifter.v
proc
write_edif result.out
backends_reviewed/write_firrtl/write_firrtl_dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_firrtl result.out
backends_reviewed/write_firrtl/write_firrtl_mux.pat 0 → 100644
_auto_pmuxtree_cc_37_or_generator_27 <= orr(pad(cat(_auto_rtlil_cc_1875_Or_16, cat(_procmux_5_CMP, _procmux_6_CMP)), 1))
_auto_pmuxtree_cc_65_recursive_mux_generator_25 <= mux(_auto_rtlil_cc_1875_Or_24, _auto_rtlil_cc_1918_Mux_20, _auto_rtlil_cc_1918_Mux_22)
_auto_pmuxtree_cc_35_or_generator_23 <= or(_procmux_8_CMP, asUInt(_procmux_7_CMP))
_auto_pmuxtree_cc_65_recursive_mux_generator_21 <= mux(_procmux_9_CMP, bits(D, 1, 1), bits(D, 0, 0))
_auto_pmuxtree_cc_65_recursive_mux_generator_19 <= mux(_procmux_7_CMP, bits(D, 3, 3), bits(D, 2, 2))
_auto_pmuxtree_cc_65_recursive_mux_generator_17 <= mux(_auto_rtlil_cc_1875_Or_16, _auto_rtlil_cc_1918_Mux_12, _auto_rtlil_cc_1918_Mux_14)
_auto_pmuxtree_cc_35_or_generator_15 <= or(_procmux_4_CMP, asUInt(_procmux_3_CMP))
_auto_pmuxtree_cc_65_recursive_mux_generator_13 <= mux(_procmux_5_CMP, bits(D, 5, 5), bits(D, 4, 4))
_auto_pmuxtree_cc_65_recursive_mux_generator_11 <= mux(_procmux_3_CMP, bits(D, 7, 7), bits(D, 6, 6))
_procmux_10_CMP0 <= eq(S, asUInt(UInt<3>("h0")))
_procmux_9_CMP0 <= eq(S, asUInt(UInt<3>("h1")))
_procmux_8_CMP0 <= eq(S, asUInt(UInt<3>("h2")))
_procmux_7_CMP0 <= eq(S, asUInt(UInt<3>("h3")))
_procmux_6_CMP0 <= eq(S, asUInt(UInt<3>("h4")))
_procmux_5_CMP0 <= eq(S, asUInt(UInt<3>("h5")))
_procmux_4_CMP0 <= eq(S, asUInt(UInt<3>("h6")))
_auto_pmuxtree_cc_65_recursive_mux_generator_29 <= mux(_auto_rtlil_cc_1848_ReduceOr_28, _auto_rtlil_cc_1918_Mux_18, _auto_rtlil_cc_1918_Mux_26)
_procmux_3_CMP0 <= eq(S, asUInt(UInt<3>("h7")))
backends_reviewed/write_firrtl/write_firrtl_mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_firrtl result.out
backends_reviewed/write_firrtl/write_firrtl_tribuf.pat 0 → 100644
_ternary_______common_tribuf_v_7_2 <= mux(en, i, UInt<1>("h0"))
backends_reviewed/write_firrtl/write_firrtl_tribuf.ys 0 → 100644
read_verilog ../../common/tribuf.v
proc
write_firrtl result.out
backends_reviewed/write_ilang/write_ilang__add_sub.pat 0 → 100644
cell $add $add$../../common/add_sub.v:10$1
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \x
connect \B \y
connect \Y $add$../../common/add_sub.v:10$1_Y
end
attribute \src "../../common/add_sub.v:11"
cell $sub $sub$../../common/add_sub.v:11$2
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \x
connect \B \y
connect \Y $sub$../../common/add_sub.v:11$2_Y
end
backends_reviewed/write_ilang/write_ilang__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__adffs.pat 0 → 100644
cell $adff $procdff$3
parameter \ARST_POLARITY 1'1
parameter \ARST_VALUE 1'0
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \ARST \clr
connect \CLK \clk
connect \D \d
connect \Q \q
end
backends_reviewed/write_ilang/write_ilang__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__dffs.pat 0 → 100644
cell $dff $procdff$2
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \clk
connect \D \d
connect \Q \q
end
backends_reviewed/write_ilang/write_ilang__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__latches.pat 0 → 100644
cell $dlatch $auto$proc_dlatch.cc:409:proc_dlatch$14
parameter \EN_POLARITY 1
parameter \WIDTH 1
connect \D $procmux$2_Y
connect \EN $auto$rtlil.cc:1844:Not$13
connect \Q \q
end
backends_reviewed/write_ilang/write_ilang__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__mul.pat 0 → 100644
cell $mul $mul$../../common/mul.v:8$1
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 12
connect \A \x
connect \B \y
connect \Y $mul$../../common/mul.v:8$1_Y
end
backends_reviewed/write_ilang/write_ilang__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__mux.pat 0 → 100644
cell $pmux $procmux$2
parameter \S_WIDTH 8
parameter \WIDTH 1
connect \A 1'x
connect \B { \D [0] \D [1] \D [2] \D [3] \D [4] \D [5] \D [6] \D [7] }
connect \S { $procmux$10_CMP $procmux$9_CMP $procmux$8_CMP $procmux$7_CMP $procmux$6_CMP $procmux$5_CMP $procmux$4_CMP $procmux$3_CMP }
connect \Y $procmux$2_Y
end
backends_reviewed/write_ilang/write_ilang__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang_mem.pat 0 → 100644
cell $mem \ram
parameter \ABITS 6
parameter \INIT 512'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
parameter \MEMID "\\ram"
parameter \OFFSET 0
parameter \RD_CLK_ENABLE 2'00
parameter \RD_CLK_POLARITY 2'00
parameter \RD_PORTS 2
parameter \RD_TRANSPARENT 2'00
parameter \SIZE 64
parameter \WIDTH 8
parameter \WR_CLK_ENABLE 2'11
parameter \WR_CLK_POLARITY 2'11
parameter \WR_PORTS 2
connect \RD_ADDR { \addr_b \addr_a }
connect \RD_CLK 2'xx
connect \RD_DATA { $memrd$\ram$../top_mem.v:40$12_DATA $memrd$\ram$../top_mem.v:26$7_DATA }
connect \RD_EN 2'xx
connect \WR_ADDR { $0$memwr$\ram$../top_mem.v:35$2_ADDR[5:0]$9 $0$memwr$\ram$../top_mem.v:21$1_ADDR[5:0]$4 }
connect \WR_CLK { \clkb \clka }
connect \WR_DATA { $0$memwr$\ram$../top_mem.v:35$2_DATA[7:0]$10 $0$memwr$\ram$../top_mem.v:21$1_DATA[7:0]$5 }
connect \WR_EN { $0$memwr$\ram$../top_mem.v:35$2_EN[7:0]$11 $0$memwr$\ram$../top_mem.v:21$1_EN[7:0]$6 }
end
backends_reviewed/write_ilang/write_ilang_tri.pat 0 → 100644
cell $mux $ternary$../top_tri.v:10$2
parameter \WIDTH 1
connect \A 1'z
connect \B \en
connect \S \i
connect \Y $ternary$../top_tri.v:10$2_Y
end
attribute \src "../top_tri.v:8"
cell $mux $ternary$../top_tri.v:8$1
parameter \WIDTH 1
connect \A 1'z
connect \B \i
connect \S \en
connect \Y $ternary$../top_tri.v:8$1_Y
end
backends_reviewed/write_intersynth/write_intersynth__latches.pat 0 → 100644
node $auto$proc_dlatch.cc:409:proc_dlatch$14 $dlatch Q q D $procmux$2_Y EN $auto$rtlil.cc:1844:Not$13 WIDTH 0x1 EN_POLARITY 0x1
node $auto$proc_dlatch.cc:409:proc_dlatch$12 $not Y $auto$rtlil.cc:1844:Not$13 A $auto$rtlil.cc:1848:ReduceOr$11 Y_WIDTH 0x1 A_WIDTH 0x1 A_SIGNED 0x0
backends_reviewed/write_intersynth/write_intersynth__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_intersynth result.out
backends_reviewed/write_intersynth/write_intersynth__memory.pat 0 → 100644
node ram $mem RD_EN CONST_1_0x0 RD_DATA $memrd$\\ram$../../common/memory.v:19$6_DATA RD_ADDR addr_a RD_CLK CONST_1_0x0 WR_EN $memwr$\\ram$../../common/memory.v:16$1_EN WR_DATA $memwr$\\ram$../../common/memory.v:16$1_DATA WR_ADDR $memwr$\\ram$../../common/memory.v:16$1_ADDR WR_CLK CONST_1_0x0 RD_TRANSPARENT '0 RD_CLK_POLARITY '0 RD_CLK_ENABLE '0 RD_PORTS 0x1 WR_CLK_POLARITY '0 WR_CLK_ENABLE '0 WR_PORTS 0x1 INIT '00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ABITS 0x6 SIZE 0x40 OFFSET 0x0 WIDTH 0x8 MEMID 0x5c72616d
backends_reviewed/write_intersynth/write_intersynth__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory_collect
write_intersynth result.out
backends_reviewed/write_intersynth/write_intersynth__mul.pat 0 → 100644
node $mul$../../common/mul.v:8$1 $mul Y $mul$../../common/mul.v:8$1_Y B y A x Y_WIDTH 0xc B_WIDTH 0x6 A_WIDTH 0x6 B_SIGNED 0x0 A_SIGNED 0x0
backends_reviewed/write_intersynth/write_intersynth__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_intersynth result.out
backends_reviewed/write_intersynth/write_intersynth__tribuf.pat 0 → 100644
node $ternary$../../common/tribuf.v:7$2 $mux Y $ternary$../../common/tribuf.v:7$2_Y S en B i A CONST_1_0x0 WIDTH 0x1
backends_reviewed/write_intersynth/write_intersynth__tribuf.ys 0 → 100644
read_verilog ../../common/tribuf.v
proc
write_intersynth result.out
backends_reviewed/write_json/write_json__adffs.pat 0 → 100644
"cells": {
"$procdff$3": {
"hide_name": 1,
"type": "$adff",
"parameters": {
"ARST_POLARITY": "1",
"ARST_VALUE": "0",
"CLK_POLARITY": "1",
"WIDTH": 1
},
"attributes": {
"src": "../../common/adffs.v:5"
},
"port_directions": {
"ARST": "input",
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"ARST": \[ 4 \],
"CLK": \[ 3 \],
"D": \[ 2 \],
"Q": \[ 5 \]
}
}
},
backends_reviewed/write_json/write_json__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__dffs.pat 0 → 100644
"cells": {
"$procdff$2": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": "1",
"WIDTH": 1
},
"attributes": {
"src": "../../common/dffs.v:2"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": \[ 3 \],
"D": \[ 2 \],
"Q": \[ 4 \]
}
}
},
backends_reviewed/write_json/write_json__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__latches.pat 0 → 100644
"$auto$proc_dlatch.cc:409:proc_dlatch$14": {
"hide_name": 1,
"type": "$dlatch",
"parameters": {
"EN_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "../../common/latches.v:2"
},
"port_directions": {
"D": "input",
"EN": "input",
"Q": "output"
},
"connections": {
"D": \[ 11 \],
"EN": \[ 10 \],
"Q": \[ 5 \]
}
},
backends_reviewed/write_json/write_json__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__memory.pat 0 → 100644
"ram": {
"hide_name": 0,
"type": "$mem",
"parameters": {
"ABITS": 6,
"INIT": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
"MEMID": "\\ram",
"OFFSET": 0,
"RD_CLK_ENABLE": "0",
"RD_CLK_POLARITY": "0",
"RD_PORTS": 1,
"RD_TRANSPARENT": "0",
"SIZE": 64,
"WIDTH": 8,
"WR_CLK_ENABLE": "0",
"WR_CLK_POLARITY": "0",
"WR_PORTS": 1
},
"attributes": {
},
"port_directions": {
"RD_ADDR": "input",
"RD_CLK": "input",
"RD_DATA": "output",
"RD_EN": "input",
"WR_ADDR": "input",
"WR_CLK": "input",
"WR_DATA": "input",
"WR_EN": "input"
},
"connections": {
"RD_ADDR": \[ 10, 11, 12, 13, 14, 15 \],
"RD_CLK": \[ "x" \],
"RD_DATA": \[ 26, 27, 28, 29, 30, 31, 32, 33 \],
"RD_EN": \[ "x" \],
"WR_ADDR": \[ 40, 41, 42, 43, 44, 45 \],
"WR_CLK": \[ "x" \],
"WR_DATA": \[ 54, 55, 56, 57, 58, 59, 60, 61 \],
"WR_EN": \[ 70, 71, 72, 73, 74, 75, 76, 77 \]
}
}
backends_reviewed/write_json/write_json__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory_collect
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__mul.pat 0 → 100644
"cells": {
"$mul$../../common/mul.v:8$1": {
"hide_name": 1,
"type": "$mul",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 6,
"B_SIGNED": 0,
"B_WIDTH": 6,
"Y_WIDTH": 12
},
"attributes": {
"src": "../../common/mul.v:8"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": \[ 2, 3, 4, 5, 6, 7 \],
"B": \[ 8, 9, 10, 11, 12, 13 \],
"Y": \[ 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 \]
}
}
},
backends_reviewed/write_json/write_json__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__mux.pat 0 → 100644
"$procmux$2": {
"hide_name": 1,
"type": "$pmux",
"parameters": {
"S_WIDTH": 8,
"WIDTH": 1
},
"attributes": {
"full_case": 1,
"src": "../../common/mux.v:20|../../common/mux.v:12"
},
"port_directions": {
"A": "input",
"B": "input",
"S": "input",
"Y": "output"
},
"connections": {
"A": \[ "x" \],
"B": \[ 12, 11, 10, 9, 8, 7, 6, 5 \],
"S": \[ 15, 16, 17, 18, 19, 20, 21, 14 \],
"Y": \[ 13 \]
}
},
backends_reviewed/write_json/write_json__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__tribuf.pat 0 → 100644
"cells": {
"$ternary$../../common/tribuf.v:7$2": {
"hide_name": 1,
"type": "$mux",
"parameters": {
"WIDTH": 1
},
"attributes": {
"src": "../../common/tribuf.v:7"
},
"port_directions": {
"A": "input",
"B": "input",
"S": "input",
"Y": "output"
},
"connections": {
"A": \[ "z" \],
"B": \[ 3 \],
"S": \[ 2 \],
"Y": \[ 4 \]
}
}
},
backends_reviewed/write_json/write_json__tribuf.ys 0 → 100644
read_verilog ../../common/tribuf.v
proc
write_json result.out
design -reset
read_json result.out
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