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yosys-tests
Commit ea6ece16 by SergeyDegtyar
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Additional tests for 'backends' group.

parent 78573f91
Showing with 1153 additions and 28 deletions
backends_reviewed/common/add_sub.v 0 → 100644
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
endmodule
backends_reviewed/common/adffs.v 0 → 100644
module top( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
backends_reviewed/common/counter.v 0 → 100644
module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset)
out <= 8'b0;
else
out <= out + 1;
endmodule
backends_reviewed/common/dffs.v 0 → 100644
module top ( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
backends_reviewed/common/latches.v 0 → 100644
module top ( input d, clk, en, output reg q );
always @*
if ( en )
q <= d;
endmodule
backends_reviewed/common/logic.v 0 → 100644
module top
(
input [0:7] in,
output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
);
assign B1 = in[0] & in[1];
assign B2 = in[0] | in[1];
assign B3 = in[0] ~& in[1];
assign B4 = in[0] ~| in[1];
assign B5 = in[0] ^ in[1];
assign B6 = in[0] ~^ in[1];
assign B7 = ~in[0];
assign B8 = in[0];
assign B9 = in[0:1] && in [2:3];
assign B10 = in[0:1] || in [2:3];
endmodule
backends_reviewed/write_blif/top_mem.v → backends_reviewed/common/memory.v
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clk)
begin
......@@ -21,24 +16,6 @@ module top
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
q_a <= ram[addr_a];
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends_reviewed/common/mul.v 0 → 100644
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule
backends_reviewed/common/mux.v 0 → 100644
module top ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
backends_reviewed/common/shifter.v 0 → 100644
module top(out, clk, in);
output [7:0] out;
input signed clk, in;
reg signed [7:0] out = 0;
always @(posedge clk)
begin
out <= out >> 1;
out[7] <= in;
end
endmodule
backends_reviewed/common/tribuf.v 0 → 100644
module top(en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
backends_reviewed/write_aiger/write_aiger__add_sub.pat 0 → 100644
aig 72 8 0 8 64
22
38
58
78
85
104
124
144
backends_reviewed/write_aiger/write_aiger__add_sub.ys 0 → 100644
read_verilog -sv ../../common/add_sub.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__adffs.ys 0 → 100644
read_verilog -sv ../../common/adffs.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__counter.ys 0 → 100644
read_verilog -sv ../../common/counter.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__dffs.ys 0 → 100644
read_verilog -sv ../../common/dffs.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__latches.ys 0 → 100644
read_verilog -sv ../../common/latches.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__logic.pat 0 → 100644
aig 24 8 0 10 16
18
21
23
24
30
37
17
16
42
49
backends_reviewed/write_aiger/write_aiger__logic.ys 0 → 100644
read_verilog -sv ../../common/logic.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__mux.ys 0 → 100644
read_verilog -sv ../../common/mux.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_aiger/write_aiger__tribuf.ys 0 → 100644
read_verilog -sv ../../common/tribuf.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends_reviewed/write_btor/write_btor__add_sub.pat 0 → 100644
4 sub 1 3 2
5 output 4 B
6 add 1 3 2
7 output 6 A
backends_reviewed/write_btor/write_btor__add_sub.ys 0 → 100644
read_verilog -sv ../../common/add_sub.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__dffs.pat 0 → 100644
1 sort bitvec 1
2 input 1 clk
3 input 1 d
4 state 1
5 output 4 q
6 next 1 4 3
backends_reviewed/write_btor/write_btor__dffs.ys 0 → 100644
read_verilog -sv ../../common/dffs.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__logic.pat 0 → 100644
13 and 3 11 12
14 output 13 B9
15 slice 3 2 7 7
16 output 15 B8
17 not 3 15
18 output 17 B7
19 slice 3 2 6 6
20 xnor 3 15 19
21 output 20 B6
22 xor 3 15 19
23 output 22 B5
24 or 3 15 19
25 not 3 24
26 output 25 B4
27 and 3 15 19
28 not 3 27
29 output 28 B3
30 or 3 15 19
31 output 30 B2
32 and 3 15 19
33 output 32 B1
backends_reviewed/write_btor/write_btor__logic.ys 0 → 100644
read_verilog -sv ../../common/logic.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__mul.ys 0 → 100644
read_verilog -sv ../../common/mul.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__shifter.ys 0 → 100644
read_verilog -sv ../../common/shifter.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_btor/write_btor__tribuf.ys 0 → 100644
read_verilog -sv ../../common/tribuf.v
hierarchy -top top
proc
write_btor result.out
backends_reviewed/write_edif/write_edif__add_sub.pat 0 → 100644
(cell (rename id00001 "$add")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 4) (direction INPUT))
(port (array B 4) (direction INPUT))
(port (array Y 4) (direction OUTPUT))
)
)
)
(cell (rename id00002 "$sub")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 4) (direction INPUT))
(port (array B 4) (direction INPUT))
(port (array Y 4) (direction OUTPUT))
)
)
)
backends_reviewed/write_edif/write_edif__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__adffs.pat 0 → 100644
(cell (rename id00001 "$adff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port ARST (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__counter.pat 0 → 100644
(cell (rename id00001 "$add")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 8) (direction INPUT))
(port (array B 32) (direction INPUT))
(port (array Y 32) (direction OUTPUT))
)
)
)
(cell (rename id00002 "$adff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port ARST (direction INPUT))
(port (array Q 8) (direction OUTPUT))
(port (array D 8) (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__counter.ys 0 → 100644
read_verilog ../../common/counter.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__dffs.pat 0 → 100644
(cell (rename id00001 "$dff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__latches.pat 0 → 100644
(cell (rename id00005 "$dlatch")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port EN (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__logic.pat 0 → 100644
(cell (rename id00001 "$not")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00002 "$and")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00003 "$or")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00004 "$xor")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00005 "$xnor")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00006 "$logic_and")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 2) (direction INPUT))
(port (array B 2) (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00007 "$logic_or")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 2) (direction INPUT))
(port (array B 2) (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
backends_reviewed/write_edif/write_edif__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__mul.pat 0 → 100644
(cell (rename id00001 "$mul")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 6) (direction INPUT))
(port (array B 6) (direction INPUT))
(port (array Y 12) (direction OUTPUT))
)
)
)
backends_reviewed/write_edif/write_edif__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__mux.pat 0 → 100644
(cell (rename id00001 "$eq")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 3) (direction INPUT))
(port (array B 3) (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00002 "$pmux")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port (array B 8) (direction INPUT))
(port Y (direction OUTPUT))
(port (array S 8) (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_edif result.out
backends_reviewed/write_edif/write_edif__shifter.pat 0 → 100644
(cell (rename id00001 "$shr")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 8) (direction INPUT))
(port (array B 32) (direction INPUT))
(port (array Y 8) (direction OUTPUT))
)
)
)
(cell (rename id00002 "$dff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port (array Q 8) (direction OUTPUT))
(port (array D 8) (direction INPUT))
)
)
)
backends_reviewed/write_edif/write_edif__shifter.ys 0 → 100644
read_verilog ../../common/shifter.v
proc
write_edif result.out
backends_reviewed/write_firrtl/write_firrtl_dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_firrtl result.out
backends_reviewed/write_firrtl/write_firrtl_mux.pat 0 → 100644
_auto_pmuxtree_cc_37_or_generator_27 <= orr(pad(cat(_auto_rtlil_cc_1875_Or_16, cat(_procmux_5_CMP, _procmux_6_CMP)), 1))
_auto_pmuxtree_cc_65_recursive_mux_generator_25 <= mux(_auto_rtlil_cc_1875_Or_24, _auto_rtlil_cc_1918_Mux_20, _auto_rtlil_cc_1918_Mux_22)
_auto_pmuxtree_cc_35_or_generator_23 <= or(_procmux_8_CMP, asUInt(_procmux_7_CMP))
_auto_pmuxtree_cc_65_recursive_mux_generator_21 <= mux(_procmux_9_CMP, bits(D, 1, 1), bits(D, 0, 0))
_auto_pmuxtree_cc_65_recursive_mux_generator_19 <= mux(_procmux_7_CMP, bits(D, 3, 3), bits(D, 2, 2))
_auto_pmuxtree_cc_65_recursive_mux_generator_17 <= mux(_auto_rtlil_cc_1875_Or_16, _auto_rtlil_cc_1918_Mux_12, _auto_rtlil_cc_1918_Mux_14)
_auto_pmuxtree_cc_35_or_generator_15 <= or(_procmux_4_CMP, asUInt(_procmux_3_CMP))
_auto_pmuxtree_cc_65_recursive_mux_generator_13 <= mux(_procmux_5_CMP, bits(D, 5, 5), bits(D, 4, 4))
_auto_pmuxtree_cc_65_recursive_mux_generator_11 <= mux(_procmux_3_CMP, bits(D, 7, 7), bits(D, 6, 6))
_procmux_10_CMP0 <= eq(S, asUInt(UInt<3>("h0")))
_procmux_9_CMP0 <= eq(S, asUInt(UInt<3>("h1")))
_procmux_8_CMP0 <= eq(S, asUInt(UInt<3>("h2")))
_procmux_7_CMP0 <= eq(S, asUInt(UInt<3>("h3")))
_procmux_6_CMP0 <= eq(S, asUInt(UInt<3>("h4")))
_procmux_5_CMP0 <= eq(S, asUInt(UInt<3>("h5")))
_procmux_4_CMP0 <= eq(S, asUInt(UInt<3>("h6")))
_auto_pmuxtree_cc_65_recursive_mux_generator_29 <= mux(_auto_rtlil_cc_1848_ReduceOr_28, _auto_rtlil_cc_1918_Mux_18, _auto_rtlil_cc_1918_Mux_26)
_procmux_3_CMP0 <= eq(S, asUInt(UInt<3>("h7")))
backends_reviewed/write_firrtl/write_firrtl_mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_firrtl result.out
backends_reviewed/write_firrtl/write_firrtl_tribuf.pat 0 → 100644
_ternary_______common_tribuf_v_7_2 <= mux(en, i, UInt<1>("h0"))
backends_reviewed/write_firrtl/write_firrtl_tribuf.ys 0 → 100644
read_verilog ../../common/tribuf.v
proc
write_firrtl result.out
backends_reviewed/write_ilang/write_ilang__add_sub.pat 0 → 100644
cell $add $add$../../common/add_sub.v:10$1
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \x
connect \B \y
connect \Y $add$../../common/add_sub.v:10$1_Y
end
attribute \src "../../common/add_sub.v:11"
cell $sub $sub$../../common/add_sub.v:11$2
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \x
connect \B \y
connect \Y $sub$../../common/add_sub.v:11$2_Y
end
backends_reviewed/write_ilang/write_ilang__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__adffs.pat 0 → 100644
cell $adff $procdff$3
parameter \ARST_POLARITY 1'1
parameter \ARST_VALUE 1'0
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \ARST \clr
connect \CLK \clk
connect \D \d
connect \Q \q
end
backends_reviewed/write_ilang/write_ilang__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__dffs.pat 0 → 100644
cell $dff $procdff$2
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \clk
connect \D \d
connect \Q \q
end
backends_reviewed/write_ilang/write_ilang__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__latches.pat 0 → 100644
cell $dlatch $auto$proc_dlatch.cc:409:proc_dlatch$14
parameter \EN_POLARITY 1
parameter \WIDTH 1
connect \D $procmux$2_Y
connect \EN $auto$rtlil.cc:1844:Not$13
connect \Q \q
end
backends_reviewed/write_ilang/write_ilang__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__mul.pat 0 → 100644
cell $mul $mul$../../common/mul.v:8$1
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 12
connect \A \x
connect \B \y
connect \Y $mul$../../common/mul.v:8$1_Y
end
backends_reviewed/write_ilang/write_ilang__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang__mux.pat 0 → 100644
cell $pmux $procmux$2
parameter \S_WIDTH 8
parameter \WIDTH 1
connect \A 1'x
connect \B { \D [0] \D [1] \D [2] \D [3] \D [4] \D [5] \D [6] \D [7] }
connect \S { $procmux$10_CMP $procmux$9_CMP $procmux$8_CMP $procmux$7_CMP $procmux$6_CMP $procmux$5_CMP $procmux$4_CMP $procmux$3_CMP }
connect \Y $procmux$2_Y
end
backends_reviewed/write_ilang/write_ilang__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends_reviewed/write_ilang/write_ilang_mem.pat 0 → 100644
cell $mem \ram
parameter \ABITS 6
parameter \INIT 512'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
parameter \MEMID "\\ram"
parameter \OFFSET 0
parameter \RD_CLK_ENABLE 2'00
parameter \RD_CLK_POLARITY 2'00
parameter \RD_PORTS 2
parameter \RD_TRANSPARENT 2'00
parameter \SIZE 64
parameter \WIDTH 8
parameter \WR_CLK_ENABLE 2'11
parameter \WR_CLK_POLARITY 2'11
parameter \WR_PORTS 2
connect \RD_ADDR { \addr_b \addr_a }
connect \RD_CLK 2'xx
connect \RD_DATA { $memrd$\ram$../top_mem.v:40$12_DATA $memrd$\ram$../top_mem.v:26$7_DATA }
connect \RD_EN 2'xx
connect \WR_ADDR { $0$memwr$\ram$../top_mem.v:35$2_ADDR[5:0]$9 $0$memwr$\ram$../top_mem.v:21$1_ADDR[5:0]$4 }
connect \WR_CLK { \clkb \clka }
connect \WR_DATA { $0$memwr$\ram$../top_mem.v:35$2_DATA[7:0]$10 $0$memwr$\ram$../top_mem.v:21$1_DATA[7:0]$5 }
connect \WR_EN { $0$memwr$\ram$../top_mem.v:35$2_EN[7:0]$11 $0$memwr$\ram$../top_mem.v:21$1_EN[7:0]$6 }
end
backends_reviewed/write_ilang/write_ilang_tri.pat 0 → 100644
cell $mux $ternary$../top_tri.v:10$2
parameter \WIDTH 1
connect \A 1'z
connect \B \en
connect \S \i
connect \Y $ternary$../top_tri.v:10$2_Y
end
attribute \src "../top_tri.v:8"
cell $mux $ternary$../top_tri.v:8$1
parameter \WIDTH 1
connect \A 1'z
connect \B \i
connect \S \en
connect \Y $ternary$../top_tri.v:8$1_Y
end
backends_reviewed/write_intersynth/write_intersynth__latches.pat 0 → 100644
node $auto$proc_dlatch.cc:409:proc_dlatch$14 $dlatch Q q D $procmux$2_Y EN $auto$rtlil.cc:1844:Not$13 WIDTH 0x1 EN_POLARITY 0x1
node $auto$proc_dlatch.cc:409:proc_dlatch$12 $not Y $auto$rtlil.cc:1844:Not$13 A $auto$rtlil.cc:1848:ReduceOr$11 Y_WIDTH 0x1 A_WIDTH 0x1 A_SIGNED 0x0
backends_reviewed/write_intersynth/write_intersynth__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_intersynth result.out
backends_reviewed/write_intersynth/write_intersynth__memory.pat 0 → 100644
node ram $mem RD_EN CONST_1_0x0 RD_DATA $memrd$\\ram$../../common/memory.v:19$6_DATA RD_ADDR addr_a RD_CLK CONST_1_0x0 WR_EN $memwr$\\ram$../../common/memory.v:16$1_EN WR_DATA $memwr$\\ram$../../common/memory.v:16$1_DATA WR_ADDR $memwr$\\ram$../../common/memory.v:16$1_ADDR WR_CLK CONST_1_0x0 RD_TRANSPARENT '0 RD_CLK_POLARITY '0 RD_CLK_ENABLE '0 RD_PORTS 0x1 WR_CLK_POLARITY '0 WR_CLK_ENABLE '0 WR_PORTS 0x1 INIT '00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ABITS 0x6 SIZE 0x40 OFFSET 0x0 WIDTH 0x8 MEMID 0x5c72616d
backends_reviewed/write_intersynth/write_intersynth__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory_collect
write_intersynth result.out
backends_reviewed/write_intersynth/write_intersynth__mul.pat 0 → 100644
node $mul$../../common/mul.v:8$1 $mul Y $mul$../../common/mul.v:8$1_Y B y A x Y_WIDTH 0xc B_WIDTH 0x6 A_WIDTH 0x6 B_SIGNED 0x0 A_SIGNED 0x0
backends_reviewed/write_intersynth/write_intersynth__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_intersynth result.out
backends_reviewed/write_intersynth/write_intersynth__tribuf.pat 0 → 100644
node $ternary$../../common/tribuf.v:7$2 $mux Y $ternary$../../common/tribuf.v:7$2_Y S en B i A CONST_1_0x0 WIDTH 0x1
backends_reviewed/write_intersynth/write_intersynth__tribuf.ys 0 → 100644
read_verilog ../../common/tribuf.v
proc
write_intersynth result.out
backends_reviewed/write_json/write_json__adffs.pat 0 → 100644
"cells": {
"$procdff$3": {
"hide_name": 1,
"type": "$adff",
"parameters": {
"ARST_POLARITY": "1",
"ARST_VALUE": "0",
"CLK_POLARITY": "1",
"WIDTH": 1
},
"attributes": {
"src": "../../common/adffs.v:5"
},
"port_directions": {
"ARST": "input",
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"ARST": \[ 4 \],
"CLK": \[ 3 \],
"D": \[ 2 \],
"Q": \[ 5 \]
}
}
},
backends_reviewed/write_json/write_json__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__dffs.pat 0 → 100644
"cells": {
"$procdff$2": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": "1",
"WIDTH": 1
},
"attributes": {
"src": "../../common/dffs.v:2"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": \[ 3 \],
"D": \[ 2 \],
"Q": \[ 4 \]
}
}
},
backends_reviewed/write_json/write_json__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__latches.pat 0 → 100644
"$auto$proc_dlatch.cc:409:proc_dlatch$14": {
"hide_name": 1,
"type": "$dlatch",
"parameters": {
"EN_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "../../common/latches.v:2"
},
"port_directions": {
"D": "input",
"EN": "input",
"Q": "output"
},
"connections": {
"D": \[ 11 \],
"EN": \[ 10 \],
"Q": \[ 5 \]
}
},
backends_reviewed/write_json/write_json__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__memory.pat 0 → 100644
"ram": {
"hide_name": 0,
"type": "$mem",
"parameters": {
"ABITS": 6,
"INIT": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
"MEMID": "\\ram",
"OFFSET": 0,
"RD_CLK_ENABLE": "0",
"RD_CLK_POLARITY": "0",
"RD_PORTS": 1,
"RD_TRANSPARENT": "0",
"SIZE": 64,
"WIDTH": 8,
"WR_CLK_ENABLE": "0",
"WR_CLK_POLARITY": "0",
"WR_PORTS": 1
},
"attributes": {
},
"port_directions": {
"RD_ADDR": "input",
"RD_CLK": "input",
"RD_DATA": "output",
"RD_EN": "input",
"WR_ADDR": "input",
"WR_CLK": "input",
"WR_DATA": "input",
"WR_EN": "input"
},
"connections": {
"RD_ADDR": \[ 10, 11, 12, 13, 14, 15 \],
"RD_CLK": \[ "x" \],
"RD_DATA": \[ 26, 27, 28, 29, 30, 31, 32, 33 \],
"RD_EN": \[ "x" \],
"WR_ADDR": \[ 40, 41, 42, 43, 44, 45 \],
"WR_CLK": \[ "x" \],
"WR_DATA": \[ 54, 55, 56, 57, 58, 59, 60, 61 \],
"WR_EN": \[ 70, 71, 72, 73, 74, 75, 76, 77 \]
}
}
backends_reviewed/write_json/write_json__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory_collect
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__mul.pat 0 → 100644
"cells": {
"$mul$../../common/mul.v:8$1": {
"hide_name": 1,
"type": "$mul",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 6,
"B_SIGNED": 0,
"B_WIDTH": 6,
"Y_WIDTH": 12
},
"attributes": {
"src": "../../common/mul.v:8"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": \[ 2, 3, 4, 5, 6, 7 \],
"B": \[ 8, 9, 10, 11, 12, 13 \],
"Y": \[ 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 \]
}
}
},
backends_reviewed/write_json/write_json__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__mux.pat 0 → 100644
"$procmux$2": {
"hide_name": 1,
"type": "$pmux",
"parameters": {
"S_WIDTH": 8,
"WIDTH": 1
},
"attributes": {
"full_case": 1,
"src": "../../common/mux.v:20|../../common/mux.v:12"
},
"port_directions": {
"A": "input",
"B": "input",
"S": "input",
"Y": "output"
},
"connections": {
"A": \[ "x" \],
"B": \[ 12, 11, 10, 9, 8, 7, 6, 5 \],
"S": \[ 15, 16, 17, 18, 19, 20, 21, 14 \],
"Y": \[ 13 \]
}
},
backends_reviewed/write_json/write_json__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_json/write_json__tribuf.pat 0 → 100644
"cells": {
"$ternary$../../common/tribuf.v:7$2": {
"hide_name": 1,
"type": "$mux",
"parameters": {
"WIDTH": 1
},
"attributes": {
"src": "../../common/tribuf.v:7"
},
"port_directions": {
"A": "input",
"B": "input",
"S": "input",
"Y": "output"
},
"connections": {
"A": \[ "z" \],
"B": \[ 3 \],
"S": \[ 2 \],
"Y": \[ 4 \]
}
}
},
backends_reviewed/write_json/write_json__tribuf.ys 0 → 100644
read_verilog ../../common/tribuf.v
proc
write_json result.out
design -reset
read_json result.out
backends_reviewed/write_smv/write_smv__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_smv result.out
backends_reviewed/write_smv/write_smv__memory.pat 0 → 100644
ASSIGN
next(_q_a) := _$memory#ram$rdreg#0#$d$149;
next(_ram#63#) := (_$memory#ram$wrmux#63##0##7#$y$2586 :: _$memory#ram$wrmux#63##0##6#$y$2582 :: _$memory#ram$wrmux#63##0##5#$y$2578 :: _$memory#ram$wrmux#63##0##4#$y$2574 :: _$memory#ram$wrmux#63##0##3#$y$2570 :: _$memory#ram$wrmux#63##0##2#$y$2566 :: _$memory#ram$wrmux#63##0##1#$y$2562 :: _$memory#ram$wrmux#63##0##0#$y$2558);
backends_reviewed/write_smv/write_smv__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory
write_smv result.out
backends_reviewed/write_smv/write_smv__mul.pat 0 → 100644
DEFINE
_$mul$######common#mul#v#8$1_Y := resize(_x, 12) * resize(_y, 12);
_A := _$mul$######common#mul#v#8$1_Y;
backends_reviewed/write_smv/write_smv__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_smv result.out
backends_reviewed/write_smv/write_smv__mux.pat 0 → 100644
DEFINE
_$procmux$10_CMP := resize(word1(resize(_S, 3) = resize(0ub3_000, 3)), 1);
_$procmux$9_CMP := resize(word1(resize(_S, 3) = resize(0ub3_001, 3)), 1);
_$procmux$8_CMP := resize(word1(resize(_S, 3) = resize(0ub3_010, 3)), 1);
_$procmux$7_CMP := resize(word1(resize(_S, 3) = resize(0ub3_011, 3)), 1);
_$procmux$6_CMP := resize(word1(resize(_S, 3) = resize(0ub3_100, 3)), 1);
_$procmux$5_CMP := resize(word1(resize(_S, 3) = resize(0ub3_101, 3)), 1);
_$procmux$4_CMP := resize(word1(resize(_S, 3) = resize(0ub3_110, 3)), 1);
_$procmux$2_Y := bool(_$procmux$3_CMP) ? _D[7:7] : bool(_$procmux$4_CMP) ? _D[6:6] : bool(_$procmux$5_CMP) ? _D[5:5] : bool(_$procmux$6_CMP) ? _D[4:4] : bool(_$procmux$7_CMP) ? _D[3:3] : bool(_$procmux$8_CMP) ? _D[2:2] : bool(_$procmux$9_CMP) ? _D[1:1] : bool(_$procmux$10_CMP) ? _D[0:0] : 0ub1_0;
_$procmux$3_CMP := resize(word1(resize(_S, 3) = resize(0ub3_111, 3)), 1);
backends_reviewed/write_smv/write_smv__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_smv result.out
backends_reviewed/write_spice/write_spice__add_sub.pat 0 → 100644
X0 1.0 1.1 1.2 1.3 y.0 y.1 y.2 y.3 x.0 x.1 x.2 x.3 _sub
X1 2.0 2.1 2.2 2.3 y.0 y.1 y.2 y.3 x.0 x.1 x.2 x.3 _add
backends_reviewed/write_spice/write_spice__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_spice result.out
backends_reviewed/write_spice/write_spice__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_spice result.out
backends_reviewed/write_spice/write_spice__counter.pat 0 → 100644
X0 clk reset out.0 out.1 out.2 out.3 out.4 out.5 out.6 out.7 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 _adff
X1 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.30 1.31 Vdd Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss out.0 out.1 out.2 out.3 out.4 out.5 out.6 out.7 _add
backends_reviewed/write_spice/write_spice__counter.ys 0 → 100644
read_verilog ../../common/counter.v
proc
write_spice result.out
backends_reviewed/write_spice/write_spice__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_spice result.out
backends_reviewed/write_spice/write_spice__latches.pat 0 → 100644
X0 q 1 2 _dlatch
X1 2 3 _not
X2 3 4 _reduce_or
X3 4 5 6 _and
X4 5 Vdd _reduce_or
X5 6 en _not
X6 1 en d d _mux
backends_reviewed/write_spice/write_spice__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_spice result.out
backends_reviewed/write_spice/write_spice__logic.pat 0 → 100644
X0 1 in.4 in.5 in.6 in.7 _logic_or
X1 2 in.4 in.5 in.6 in.7 _logic_and
X2 3 in.7 _not
X3 4 in.6 in.7 _xnor
X4 5 in.6 in.7 _xor
X5 6 7 _not
X6 7 in.6 in.7 _or
X7 8 9 _not
X8 9 in.6 in.7 _and
X9 10 in.6 in.7 _or
X10 11 in.6 in.7 _and
backends_reviewed/write_spice/write_spice__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_spice result.out
backends_reviewed/write_spice/write_spice__memory.pat 0 → 100644
X1186 1189.0 1189.1 1189.2 1189.3 1189.4 1189.5 1189.6 1189.7 q_a.0 q_a.1 q_a.2 q_a.3 q_a.4 q_a.5 q_a.6 q_a.7 clk _dff
backends_reviewed/write_spice/write_spice__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory
write_spice result.out
backends_reviewed/write_spice/write_spice__mul.pat 0 → 100644
X0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 y.0 y.1 y.2 y.3 y.4 y.5 x.0 x.1 x.2 x.3 x.4 x.5 _mul
backends_reviewed/write_spice/write_spice__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_spice result.out
backends_reviewed/write_spice/write_spice__mux.pat 0 → 100644
X0 1 Vss Vss Vss S.0 S.1 S.2 _eq
X1 2 Vdd Vss Vss S.0 S.1 S.2 _eq
X2 3 Vss Vdd Vss S.0 S.1 S.2 _eq
X3 4 Vdd Vdd Vss S.0 S.1 S.2 _eq
X4 5 Vss Vss Vdd S.0 S.1 S.2 _eq
X5 6 Vdd Vss Vdd S.0 S.1 S.2 _eq
X6 7 Vss Vdd Vdd S.0 S.1 S.2 _eq
X7 8 9 7 6 5 4 3 2 1 D.7 D.6 D.5 D.4 D.3 D.2 D.1 D.0 _NC0 _pmux
X8 9 Vdd Vdd Vdd S.0 S.1 S.2 _eq
backends_reviewed/write_spice/write_spice__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_spice result.out
backends_reviewed/write_spice/write_spice__shifter.pat 0 → 100644
X0 clk out.0 out.1 out.2 out.3 out.4 out.5 out.6 out.7 1.0 1.1 1.2 1.3 1.4 1.5 1.6 in _dff
X1 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Vdd Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss out.0 out.1 out.2 out.3 out.4 out.5 out.6 out.7 _shr
backends_reviewed/write_spice/write_spice__shifter.ys 0 → 100644
read_verilog ../../common/shifter.v
proc
write_spice result.out
backends_reviewed/write_table/write_table.pat 0 → 100644
tristate $ternary$../top.v:10$2 $mux A in 1'z
tristate $ternary$../top.v:10$2 $mux B in \\en
tristate $ternary$../top.v:10$2 $mux S in \\i
tristate $ternary$../top.v:10$2 $mux Y out $ternary$../top.v:10$2_Y
tristate $ternary$../top.v:8$1 $mux A in 1'z
tristate $ternary$../top.v:8$1 $mux B in \\i
tristate $ternary$../top.v:8$1 $mux S in \\en
tristate $ternary$../top.v:8$1 $mux Y out $ternary$../top.v:8$1_Y
backends_reviewed/write_table/write_table__add_sub.pat 0 → 100644
top $add$../../common/add_sub.v:10$1 $add A in \\x
top $add$../../common/add_sub.v:10$1 $add B in \\y
top $add$../../common/add_sub.v:10$1 $add Y out $add$../../common/add_sub.v:10$1_Y
top $sub$../../common/add_sub.v:11$2 $sub A in \\x
top $sub$../../common/add_sub.v:11$2 $sub B in \\y
top $sub$../../common/add_sub.v:11$2 $sub Y out $sub$../../common/add_sub.v:11$2_Y
backends_reviewed/write_table/write_table__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_table result.out
backends_reviewed/write_table/write_table__adffs.pat 0 → 100644
top $procdff$3 $adff ARST in \\clr
top $procdff$3 $adff CLK in \\clk
top $procdff$3 $adff D in \\d
top $procdff$3 $adff Q out \\q
backends_reviewed/write_table/write_table__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_table result.out
backends_reviewed/write_table/write_table__counter.pat 0 → 100644
top $add$../../common/counter.v:10$2 $add A in \\out
top $add$../../common/counter.v:10$2 $add B in 1
top $add$../../common/counter.v:10$2 $add Y out $add$../../common/counter.v:10$2_Y
top $procdff$3 $adff ARST in \\reset
top $procdff$3 $adff CLK in \\clk
top $procdff$3 $adff D in $add$../../common/counter.v:10$2_Y \[7:0\]
top $procdff$3 $adff Q out \\out
backends_reviewed/write_table/write_table__counter.ys 0 → 100644
read_verilog ../../common/counter.v
proc
write_table result.out
backends_reviewed/write_table/write_table__dffs.pat 0 → 100644
top $procdff$2 $dff CLK in \\clk
top $procdff$2 $dff D in \\d
top $procdff$2 $dff Q out \\q
backends_reviewed/write_table/write_table__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_table result.out
backends_reviewed/write_table/write_table__latches.pat 0 → 100644
top $auto$proc_dlatch.cc:409:proc_dlatch$14 $dlatch D in $procmux$2_Y
top $auto$proc_dlatch.cc:409:proc_dlatch$14 $dlatch EN in $auto$rtlil.cc:1844:Not$13
top $auto$proc_dlatch.cc:409:proc_dlatch$14 $dlatch Q out \\q
backends_reviewed/write_table/write_table__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_table result.out
backends_reviewed/write_table/write_table__logic.pat 0 → 100644
top $xnor$../../common/logic.v:11$8 $xnor A in \\in [7]
top $xnor$../../common/logic.v:11$8 $xnor B in \\in [6]
top $xnor$../../common/logic.v:11$8 $xnor Y out $xnor$../../common/logic.v:11$8_Y
top $xor$../../common/logic.v:10$7 $xor A in \\in [7]
top $xor$../../common/logic.v:10$7 $xor B in \\in [6]
top $xor$../../common/logic.v:10$7 $xor Y out $xor$../../common/logic.v:10$7_Y
backends_reviewed/write_table/write_table__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_table result.out
backends_reviewed/write_table/write_table__memory.pat 0 → 100644
top $memrd$\\ram$../../common/memory.v:19$6 $memrd ADDR in \\addr_a
top $memrd$\\ram$../../common/memory.v:19$6 $memrd CLK in 1'x
top $memrd$\\ram$../../common/memory.v:19$6 $memrd DATA out $memrd$\\ram$../../common/memory.v:19$6_DATA
top $memrd$\\ram$../../common/memory.v:19$6 $memrd EN in 1'x
top $memwr$\\ram$../../common/memory.v:16$7 $memwr ADDR in $memwr$\\ram$../../common/memory.v:16$1_ADDR
top $memwr$\\ram$../../common/memory.v:16$7 $memwr CLK in 1'x
top $memwr$\\ram$../../common/memory.v:16$7 $memwr DATA in $memwr$\\ram$../../common/memory.v:16$1_DATA
top $memwr$\\ram$../../common/memory.v:16$7 $memwr EN in $memwr$\\ram$../../common/memory.v:16$1_EN
backends_reviewed/write_table/write_table__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
write_table result.out
backends_reviewed/write_table/write_table__mul.pat 0 → 100644
top $mul$../../common/mul.v:8$1 $mul A in \\x
top $mul$../../common/mul.v:8$1 $mul B in \\y
top $mul$../../common/mul.v:8$1 $mul Y out $mul$../../common/mul.v:8$1_Y
backends_reviewed/write_table/write_table__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_table result.out
backends_reviewed/write_table/write_table__mux.pat 0 → 100644
top $procmux$2 $pmux B in { \\D [0] \\D [1] \\D [2] \\D [3] \\D [4] \\D [5] \\D [6] \\D [7] }
top $procmux$2 $pmux S in { $procmux$10_CMP $procmux$9_CMP $procmux$8_CMP $procmux$7_CMP $procmux$6_CMP $procmux$5_CMP $procmux$4_CMP $procmux$3_CMP }
top $procmux$2 $pmux Y out $procmux$2_Y
backends_reviewed/write_table/write_table__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_table result.out
backends_reviewed/write_table/write_table__shifter.pat 0 → 100644
top $shr$../../common/shifter.v:8$2 $shr A in \\out
top $shr$../../common/shifter.v:8$2 $shr B in 1
top $shr$../../common/shifter.v:8$2 $shr Y out $shr$../../common/shifter.v:8$2_Y
backends_reviewed/write_table/write_table__shifter.ys 0 → 100644
read_verilog ../../common/shifter.v
proc
write_table result.out
backends_reviewed/write_xaiger/write_xaiger__add_sub.pat 0 → 100644
aig 72 8 0 8 64
22
38
58
78
85
104
124
144
backends_reviewed/write_xaiger/write_xaiger__add_sub.ys 0 → 100644
read_verilog -sv ../../common/add_sub.v
aigmap
write_xaiger result.out
backends_reviewed/write_xaiger/write_xaiger__adffs.ys 0 → 100644
read_verilog -sv ../../common/adffs.v
aigmap
write_xaiger result.out
backends_reviewed/write_xaiger/write_xaiger__counter.ys 0 → 100644
read_verilog -sv ../../common/counter.v
aigmap
write_xaiger result.out
backends_reviewed/write_xaiger/write_xaiger__dffs.ys 0 → 100644
read_verilog -sv ../../common/dffs.v
aigmap
write_xaiger result.out
backends_reviewed/write_xaiger/write_xaiger__latches.ys 0 → 100644
read_verilog -sv ../../common/latches.v
aigmap
write_xaiger result.out
backends_reviewed/write_xaiger/write_xaiger__logic.pat 0 → 100644
aig 24 8 0 10 16
18
21
23
24
30
37
17
16
42
49
backends_reviewed/write_xaiger/write_xaiger__logic.ys 0 → 100644
read_verilog -sv ../../common/logic.v
aigmap
write_xaiger result.out
backends_reviewed/write_xaiger/write_xaiger__mux.ys 0 → 100644
read_verilog -sv ../../common/mux.v
aigmap
write_xaiger result.out
backends_reviewed/write_xaiger/write_xaiger__tribuf.ys 0 → 100644
read_verilog -sv ../../common/tribuf.v
aigmap
write_xaiger result.out
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