Merge remote-tracking branch 'origin/master' into xc7srl

architecture/Makefile

@@ -30,7 +30,8 @@ $(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top
 $(eval $(call template,synth_coolrunner2_fulladder,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
 
 #easic - issue #920
-$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
+# we do not have eTools anymore available, commented until aquired
+#$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
 
 #ecp5
 $(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))

architecture/common.v

 module assert_dff(input clk, input test, input pat);
     always @(posedge clk)
     begin
+        #1;
         if (test != pat)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time);
@@ -12,7 +13,7 @@ endmodule
 module assert_tri(input en, input A, input B);
     always @(posedge en)
     begin
-        //#1;
+        #1;
         if (A !== B)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
@@ -24,7 +25,7 @@ endmodule
 module assert_Z(input clk, input A);
     always @(posedge clk)
     begin
-        //#1;
+        #1;
         if (A === 1'bZ)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);

backends/common.v

 module assert_dff(input clk, input test, input pat);
     always @(posedge clk)
     begin
+        #1;
         if (test != pat)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time);
@@ -24,7 +25,7 @@ endmodule
 module assert_Z(input clk, input A);
     always @(posedge clk)
     begin
-        //#1;
+        #1;
         if (A === 1'bZ)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);

backends/write_aiger/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_blif/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_div_mod/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_logic/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_shift/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_edif/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_firrtl_logic/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_firrtl_reduce/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_firrtl_shift/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_intersynth/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_json/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smt2_init_assert/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smt2_reduce/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smv_init_assert/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smv_reduce/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_smv_shift/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_verilog_concat/testbench.v

 module testbench;
     reg [4:0] in;
 
-	wire [1:0] Ap = 0;
-	wire [2:0] Bp = 0;
-	wire [2:0] Cp = 0;
-	wire [1:0] A = 0;
-	wire [2:0] B = 0;
-	wire [2:0] C = 0;
+	wire [1:0] Ap;
+	wire [2:0] Bp;
+	wire [2:0] Cp;
+	wire [1:0] A;
+	wire [2:0] B;
+	wire [2:0] C;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/common.v

 module assert_dff(input clk, input test, input pat);
     always @(posedge clk)
     begin
+        #1;
         if (test != pat)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time);
@@ -24,7 +25,7 @@ endmodule
 module assert_Z(input clk, input A);
     always @(posedge clk)
     begin
-        //#1;
+        #1;
         if (A === 1'bZ)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);

frontends/read/testbench.v

 module testbench;
     reg [2:0] in;
 
-	wire patt_out = 0;
-	wire patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire patt_out;
+	wire patt_carry_out;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read/top.v

@@ -9,11 +9,6 @@ module top
  output cout
  );
 
- initial begin
-    A = 0;
-    cout = 0;
- end
-
 `ifndef BUG
  assign    A =  y + cin;
  assign   cout =  y + A;

frontends/read_aiger/testbench.v

 module testbench;
     reg [2:0] in;
 
-	wire patt_out = 0;
-	wire patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire patt_out;
+	wire patt_carry_out;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_aiger/top.v

@@ -9,11 +9,6 @@ module top
  output cout
  );
 
- initial begin
-    A = 0;
-    cout = 0;
- end
-
 `ifndef BUG
  assign    A =  y + cin;
  assign   cout =  y + A;

frontends/read_blif/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_blif_eblif/testbench.v

 module testbench;
     reg a;
 
-	wire b = 1'bx;
+	wire b;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_blif_logic/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_json/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty/testbench.v

 module testbench;
     reg a;
 
-	wire b = 1'bx;
+	wire b;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_arith/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_diff_inv/testbench.v

 module testbench;
     reg a;
 
-	wire b = 1'bx;
+	wire b;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff_n/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff_np/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff_pn/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_ff_pp/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_latch/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_latch_n/testbench.v

@@ -2,7 +2,7 @@ module testbench;
     reg [2:0] in;
 
 	reg patt_out = 0;
-	wire out = 0;
+	wire out;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/read_liberty_tri/testbench.v

 module testbench;
     reg a;
 	reg En = 1'b1;
-	wire b = 1'bx;
+	wire b;
 
     initial begin
         // $dumpfile("testbench.vcd");

frontends/verilog_lexer_assert_assume_restrict/top.v

@@ -5,8 +5,8 @@ module top
  input cin,
  input clk,
 
- output A,
- output cout
+ output reg A,
+ output reg cout
  );
 
  initial begin

frontends/verilog_lexer_unique_priority/top.v

@@ -85,7 +85,8 @@ input [15:0] D,
 output M2,M4,M8,M16
 );
 
-wire a,b,c,d,e,f,g,h;
+wire a,c,d,e,g;
+reg b,h,f;
 
 always @(*)
 begin

simple/common.v

 module assert_dff(input clk, input test, input pat);
     always @(posedge clk)
     begin
+        #1;
         if (test != pat)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time);
@@ -12,7 +13,7 @@ endmodule
 module assert_tri(input en, input A, input B);
     always @(posedge en)
     begin
-        //#1;
+        #1;
         if (A !== B)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
@@ -24,7 +25,7 @@ endmodule
 module assert_Z(input clk, input A);
     always @(posedge clk)
     begin
-        //#1;
+        #1;
         if (A === 1'bZ)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
@@ -36,7 +37,7 @@ endmodule
 module assert_X(input clk, input A);
     always @(posedge clk)
     begin
-        //#1;
+        #1;
         if (A === 1'bX)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);