Commit e45c8c1e by Eddie Hung

Merge remote-tracking branch 'origin/master' into xc7srl

parents 5c408f4d 753930e7
......@@ -30,7 +30,8 @@ $(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top
$(eval $(call template,synth_coolrunner2_fulladder,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
#easic - issue #920
$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
# we do not have eTools anymore available, commented until aquired
#$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
#ecp5
$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
......
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
......@@ -12,7 +13,7 @@ endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
//#1;
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
......@@ -24,7 +25,7 @@ endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
//#1;
#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
......
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
......@@ -24,7 +25,7 @@ endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
//#1;
#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -5,8 +5,8 @@ module testbench;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -5,8 +5,8 @@ module testbench;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -5,8 +5,8 @@ module testbench;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -5,8 +5,8 @@ module testbench;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -5,8 +5,8 @@ module testbench;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -5,8 +5,8 @@ module testbench;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
module testbench;
reg [4:0] in;
wire [1:0] Ap = 0;
wire [2:0] Bp = 0;
wire [2:0] Cp = 0;
wire [1:0] A = 0;
wire [2:0] B = 0;
wire [2:0] C = 0;
wire [1:0] Ap;
wire [2:0] Bp;
wire [2:0] Cp;
wire [1:0] A;
wire [2:0] B;
wire [2:0] C;
initial begin
// $dumpfile("testbench.vcd");
......
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
......@@ -24,7 +25,7 @@ endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
//#1;
#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
......
module testbench;
reg [2:0] in;
wire patt_out = 0;
wire patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire patt_out;
wire patt_carry_out;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -9,11 +9,6 @@ module top
output cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
assign A = y + cin;
assign cout = y + A;
......
module testbench;
reg [2:0] in;
wire patt_out = 0;
wire patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire patt_out;
wire patt_carry_out;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -9,11 +9,6 @@ module top
output cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
assign A = y + cin;
assign cout = y + A;
......
......@@ -5,8 +5,8 @@ module testbench;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
module testbench;
reg a;
wire b = 1'bx;
wire b;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -5,8 +5,8 @@ module testbench;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -3,8 +3,8 @@ module testbench;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
module testbench;
reg a;
wire b = 1'bx;
wire b;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -5,8 +5,8 @@ module testbench;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
......
module testbench;
reg a;
wire b = 1'bx;
wire b;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -2,7 +2,7 @@ module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -2,7 +2,7 @@ module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -2,7 +2,7 @@ module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -2,7 +2,7 @@ module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -2,7 +2,7 @@ module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -2,7 +2,7 @@ module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -2,7 +2,7 @@ module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
......
module testbench;
reg a;
reg En = 1'b1;
wire b = 1'bx;
wire b;
initial begin
// $dumpfile("testbench.vcd");
......
......@@ -5,8 +5,8 @@ module top
input cin,
input clk,
output A,
output cout
output reg A,
output reg cout
);
initial begin
......
......@@ -85,7 +85,8 @@ input [15:0] D,
output M2,M4,M8,M16
);
wire a,b,c,d,e,f,g,h;
wire a,c,d,e,g;
reg b,h,f;
always @(*)
begin
......
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
......@@ -12,7 +13,7 @@ endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
//#1;
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
......@@ -24,7 +25,7 @@ endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
//#1;
#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
......@@ -36,7 +37,7 @@ endmodule
module assert_X(input clk, input A);
always @(posedge clk)
begin
//#1;
#1;
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
......
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