Commit e1166014 by SergeyDegtyar

Review and update tests for issues 1243-1372

parent 30151c06
......@@ -16,41 +16,4 @@ clean::
rm -rf $(design)/work_$(script)
))
endef
#issue_01243
$(eval $(call template,issue_01243,issue_01243))
#issue_01273
$(eval $(call template,issue_01273,issue_01273))
#issue_01284
$(eval $(call template,issue_01284,issue_01284))
#issue_01329
$(eval $(call template,issue_01329,issue_01329))
#issue_01364
$(eval $(call template,issue_01364,issue_01364))
#issue_01372
$(eval $(call template,issue_01372,issue_01372))
#Still open bugs (should be failed):
#issue_01259
$(eval $(call template,issue_01259,issue_01259))
#issue_01291
$(eval $(call template,issue_01291,issue_01291))
#issue_01360
$(eval $(call template,issue_01360,issue_01360))
.PHONY: all clean
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
read_verilog ../top.v
synth
write_verilog -noattr result.log
tee -o result.log read_verilog ../top.v
hierarchy -top top
tee -o result.log write_smt2
read_verilog ../top.v
proc
synth -top top
extract_fa -ha -v
tee -o result.log dump
synth -top top
write_verilog synth.v
......@@ -482,6 +482,24 @@ $(eval $(call template,issue_01223,issue_01223))
#issue_01231
$(eval $(call template,issue_01231,issue_01231))
#issue_01243
$(eval $(call template,issue_01243,issue_01243))
#issue_01273
$(eval $(call template,issue_01273,issue_01273))
#issue_01284
$(eval $(call template,issue_01284,issue_01284))
#issue_01329
$(eval $(call template,issue_01329,issue_01329))
#issue_01364
$(eval $(call template,issue_01364,issue_01364))
#issue_01372
$(eval $(call template,issue_01372,issue_01372))
#Still open bugs (should be failed):
#issue_00329
......@@ -514,4 +532,13 @@ $(eval $(call template,issue_01217,issue_01217))
#issue_01225
$(eval $(call template,issue_01225,issue_01225))
#issue_01259
$(eval $(call template,issue_01259,issue_01259))
#issue_01291
$(eval $(call template,issue_01291,issue_01291))
#issue_01360
$(eval $(call template,issue_01360,issue_01360))
.PHONY: all clean
read_verilog ../top.v
synth
write_verilog -noattr result.log
write_verilog -noattr result.out
read_verilog ../top.v
hierarchy -top top
write_smt2
read_verilog ../top.v
proc
synth -top top
equiv_opt -assert extract_fa -ha -v
design -load postopt
cd top
select -assert-count 1 t:$_ANDNOT_
select -assert-count 1 t:$_AND_
select -assert-count 2 t:$_NOT_
select -assert-count 1 t:$_OR_
select -assert-count 2 t:$_XNOR_
select -assert-count 2 t:$fa
select -assert-none t:$_ANDNOT_ t:$_AND_ t:$_NOT_ t:$_OR_ t:$_XNOR_ t:$fa %% t:* %D
tee -o result.log read_verilog ../top.v
read_verilog ../top.v
proc
equiv_opt -assert prep
prep -top frozen
tee -o result.log dump
tee -o result.out dump
write_verilog top.v
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