Add test8, test9

architecture/synth_xilinx_srl/test8.v

+// Check multi-bit works
+// pos_clk_no_enable_no_init_not_inferred_N_width
+module test8 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
+generate 
+    wire [depth:0] int [width-1:0];
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        assign int[w][0] = i[w];
+        for (d = 0; d < depth; d=d+1) begin
+            \$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][w+1]));
+        end
+        assign q[w] = int[w][depth];
+    end
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test9.v

+// Check multi-bit works
+// neg_clk_no_enable_with_init_with_inferred_N_width
+module test9 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
+generate 
+    reg [depth-1:0] int [width-1:0];
+
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        for (d = 0; d < depth; d=d+1)
+            initial int[w][d] <= ~((d+w) % 2);
+
+        if (depth == 1) begin
+            always @(negedge clk) int[w] <= i[w];
+            assign q[w] = int[w];
+        end
+        else begin
+            always @(negedge clk) int[w] <= { int[w][depth-2:0], i[w] };
+            assign q[w] = int[w][depth-1];
+        end
+    end
+endgenerate
+endmodule