Test 7

architecture/synth_xilinx_srl/generate.py

@@ -3,7 +3,7 @@
 N = 131
 
 # Test 1: pos_clk_no_enable_no_init_not_inferred
-for i in range(N):
+for i in range(1,N+1):
     with open('test1_%d.v' % i, 'w') as fp:
         fp.write('''
 module test1_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
@@ -19,10 +19,10 @@ generate
     end
 endgenerate
 endmodule
-'''.format(i+1))
+'''.format(i))
 
 # Test 2: pos_clk_with_enable_no_init_not_inferred
-for i in range(N):
+for i in range(1,N+1):
     with open('test2_%d.v' % i, 'w') as fp:
         fp.write('''
 module test2_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
@@ -38,10 +38,10 @@ generate
     end
 endgenerate
 endmodule
-'''.format(i+1))
+'''.format(i))
 
 # Test 3: pos_clk_with_enable_with_init_inferred
-for i in range(N):
+for i in range(1,N+1):
     with open('test3_%d.v' % i, 'w') as fp:
         fp.write('''
 module test3_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
@@ -64,14 +64,10 @@ generate
     end
 endgenerate
 endmodule
-'''.format(i+1))
-
-    for (i = 0; i < `N; i=i+1) begin : 
-        shift_reg #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state */);
-    end
+'''.format(i))
 
 # Test 4: neg_clk_no_enable_no_init_not_inferred
-for i in range(N):
+for i in range(1,N+1):
     with open('test4_%d.v' % i, 'w') as fp:
         fp.write('''
 module test4_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
@@ -87,10 +83,10 @@ generate
     end
 endgenerate
 endmodule
-'''.format(i+1))
+'''.format(i))
 
 # Test 5: neg_clk_no_enable_no_init_inferred
-for i in range(N):
+for i in range(1,N+1):
     with open('test5_%d.v' % i, 'w') as fp:
         fp.write('''
 module test5_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
@@ -110,11 +106,10 @@ generate
     end
 endgenerate
 endmodule
-'''.format(i+1))
-
+'''.format(i))
 
 # Test 6: neg_clk_with_enable_with_init_inferred
-for i in range(N):
+for i in range(1,N+1):
     with open('test6_%d.v' % i, 'w') as fp:
         fp.write('''
 module test6_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
@@ -137,4 +132,4 @@ generate
     end
 endgenerate
 endmodule
-'''.format(i+1))
+'''.format(i))

architecture/synth_xilinx_srl/test7a.v

+// Check that use of resets block shreg
+// pos_clk_no_enable_no_init_not_inferred_with_reset
+module test7a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
+generate 
+    wire [depth:0] int [width-1:0];
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        assign int[w][0] = i[w];
+        for (d = 0; d < depth; d=d+1) begin
+            \$_DFF_PP0_ r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][w+1]));
+        end
+        assign q[w] = int[w][depth];
+    end
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test7b.v

+// Check that use of resets block shreg
+// neg_clk_no_enable_with_init_with_inferred_with_reset
+module test7b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
+generate 
+    reg [depth-1:0] int [width-1:0];
+
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        for (d = 0; d < depth; d=d+1)
+            initial int[w][d] <= ~((d+w) % 2);
+
+        if (depth == 1) begin
+            always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= i[w];
+            assign q[w] = int[w];
+        end
+        else begin
+            always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= { int[w][depth-2:0], i[w] };
+            assign q[w] = int[w][depth-1];
+        end
+    end
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test7c.v

+// Check that use of resets block shreg
+// pos_clk_no_enable_no_init_not_inferred_with_reset_var_len
+module test7c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
+generate 
+    wire [depth:0] int [width-1:0];
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        assign int[w][0] = i[w];
+        for (d = 0; d < depth; d=d+1) begin
+            \$_DFF_PP0_ r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][w+1]));
+        end
+        wire [depth-1:0] t;
+        assign t = int[w][depth:1];
+        assign q[w] = t[l];
+    end
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test7d.v

+// Check that use of resets block shreg
+// neg_clk_no_enable_with_init_with_inferred_with_reset_var_len
+module test7d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
+generate 
+    reg [depth-1:0] int [width-1:0];
+
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        for (d = 0; d < depth; d=d+1)
+            initial int[w][d] <= ~((d+w) % 2);
+
+        if (depth == 1) begin
+            always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= a[w];
+            assign q[w] = int[w];
+        end
+        else begin
+            always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= {{ int[w][depth-2:0], i[w] }};
+            assign q[w] = int[w][l];
+        end
+    end
+endgenerate
+endmodule