Fix failing tests

architecture/synth_xilinx/synth_xilinx_nocarry.ys

@@ -10,9 +10,8 @@ stat
 select -assert-count 1 t:LUT2
 select -assert-count 3 t:LUT4
 select -assert-count 4 t:LUT6
-select -assert-count 5 t:MUXCY
-select -assert-count 6 t:XORCY
-select -assert-none t:LUT2 t:LUT4 t:LUT6 t:MUXCY t:XORCY %% t:* %D
+select -assert-count 2 t:CARRY4
+select -assert-none t:LUT2 t:LUT4 t:LUT6 t:CARRY4 %% t:* %D
 
 design -load read
 hierarchy -top top

architecture/synth_xilinx/synth_xilinx_nodsp.ys

@@ -17,12 +17,11 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -noiopad # equiv
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
+select -assert-count 3 t:CARRY4
 select -assert-count 17 t:LUT2
 select -assert-count 1 t:LUT3
 select -assert-count 2 t:LUT4
 select -assert-count 2 t:LUT5
 select -assert-count 38 t:LUT6
-select -assert-count 11 t:MUXCY
 select -assert-count 4 t:MUXF7
-select -assert-count 12 t:XORCY
-select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
+select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:CARRY4 %% t:* %D

architecture/synth_xilinx/synth_xilinx_nowidelut.ys

@@ -12,10 +12,9 @@ select -assert-count 1 t:LUT3
 select -assert-count 6 t:LUT4
 select -assert-count 1 t:LUT5
 select -assert-count 33 t:LUT6
-select -assert-count 11 t:MUXCY
+select -assert-count 3 t:CARRY4
 select -assert-count 1 t:MUXF7
-select -assert-count 12 t:XORCY
-select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
+select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:CARRY4 t:MUXF7 %% t:* %D
 
 design -load read
 hierarchy -top top
@@ -24,11 +23,10 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut -noio
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 17 t:LUT2
-select -assert-count 9 t:LUT3
-select -assert-count 12 t:LUT4
-select -assert-count 7 t:LUT5
-select -assert-count 20 t:LUT6
-select -assert-count 11 t:MUXCY
-select -assert-count 12 t:XORCY
-select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:XORCY %% t:* %D
+select -assert-count 11 t:LUT2
+select -assert-count 3 t:LUT3
+select -assert-count 7 t:LUT4
+select -assert-count 2 t:LUT5
+select -assert-count 31 t:LUT6
+select -assert-count 3 t:CARRY4
+select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:CARRY4 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys

@@ -14,12 +14,12 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 design -load postopt
 cd dynpreaddmultadd
 #Vivado synthesizes 1 DSP48E1.
+stat
 select -assert-count 1 t:BUFG
 select -assert-count 16 t:FDRE
 select -assert-count 1 t:DSP48E1
 select -assert-count 32 t:LUT2
 select -assert-count 9 t:LUT3
-select -assert-count 16 t:MUXCY
-select -assert-count 18 t:XORCY
+select -assert-count 6 t:CARRY4
 
-select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:LUT3 t:MUXCY t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:LUT3 t:CARRY4 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys

@@ -20,8 +20,8 @@ select -assert-count 1 t:BUFG
 select -assert-count 16 t:FDRE
 select -assert-count 5 t:LUT2
 select -assert-count 4 t:LUT3
-select -assert-count 11 t:LUT4
-select -assert-count 25 t:LUT5
+select -assert-count 12 t:LUT4
+select -assert-count 24 t:LUT5
 select -assert-count 32 t:LUT6
 select -assert-count 128 t:RAM128X1D
 

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys

@@ -20,9 +20,9 @@ select -assert-count 1 t:BUFG
 select -assert-count 16 t:FDRE
 select -assert-count 1 t:LUT2
 select -assert-count 8 t:LUT4
-select -assert-count 36 t:LUT5
-select -assert-count 38 t:LUT6
-select -assert-count 10 t:MUXF7
+select -assert-count 40 t:LUT5
+select -assert-count 36 t:LUT6
+select -assert-count 12 t:MUXF7
 select -assert-count 128 t:RAM128X1D
 
 select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys

@@ -19,7 +19,6 @@ select -assert-count 1 t:BUFG
 select -assert-count 1 t:DSP48E1
 select -assert-count 32 t:FDRE
 select -assert-count 32 t:LUT2
-select -assert-count 16 t:MUXCY
-select -assert-count 17 t:XORCY
+select -assert-count 5 t:CARRY4
 
-select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D
+select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:CARRY4 %% t:* %D