Commit 9a201971 by Miodrag Milanovic

Fix regressions

parent 0342cd35
read_verilog ../top_dff.v
proc
dff2dffe
synth -top top
abc9 -lut 5 -nomfs
abc9 -lut 5
......@@ -2,4 +2,4 @@ read_verilog ../top.v
synth -top top
abc -lut 4
select -assert-count 32 t:$_DFF_P_
select -assert-count 689 t:$lut
select -assert-count 688 t:$lut
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