Commit c67c5284 by Eddie Hung

Add argument for -match

parent d37f4c67
read_verilog ../top.v read_verilog ../top.v
synth_greenpak4 -run begin:map_luts synth_greenpak4 -run begin:map_luts
shregmap -match -enpol any shregmap -match foobar -enpol any
design -reset design -reset
read_verilog ../top.v read_verilog ../top.v
write_verilog synth.v write_verilog synth.v
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