Test fixes

architecture/synth_ecp5/synth_ecp5_nobram.ys

@@ -34,8 +34,9 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
 design -load postopt
 cd top
-select -assert-count 144 t:LUT4
-select -assert-count 17 t:PFUMX
+stat
+select -assert-count 143 t:LUT4
+select -assert-count 16 t:PFUMX
 select -assert-count 32 t:TRELLIS_DPR16X4
 select -assert-count 143 t:TRELLIS_FF
 select -assert-none t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D

architecture/synth_ice40/synth_ice40_nobram.ys

@@ -30,8 +30,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
 design -load postopt
 cd top
-
+stat
 select -assert-count 6 t:SB_DFF
 select -assert-count 384 t:SB_DFFE
-select -assert-count 376 t:SB_LUT4
+select -assert-count 372 t:SB_LUT4
 select -assert-none t:SB_DFF t:SB_DFFE t:SB_LUT4 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys

@@ -17,13 +17,13 @@ stat
 #Vivado synthesizes 1 RAMB18E1.
 select -assert-count 2 t:BUFG
 select -assert-count 200 t:FDRE
-select -assert-count 26 t:LUT1
-select -assert-count 16 t:LUT2
-select -assert-count 49 t:LUT3
-select -assert-count 5 t:LUT4
-select -assert-count 100 t:LUT5
-select -assert-count 284 t:LUT6
-select -assert-count 341 t:MUXF7
-select -assert-count 154 t:MUXF8
+select -assert-count 27 t:LUT1
+select -assert-count 23 t:LUT2
+select -assert-count 48 t:LUT3
+select -assert-count 24 t:LUT4
+select -assert-count 138 t:LUT5
+select -assert-count 227 t:LUT6
+select -assert-count 318 t:MUXF7
+select -assert-count 142 t:MUXF8
 
 select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys

@@ -20,8 +20,8 @@ select -assert-count 1 t:BUFG
 select -assert-count 16 t:FDRE
 select -assert-count 5 t:LUT2
 select -assert-count 4 t:LUT3
-select -assert-count 12 t:LUT4
-select -assert-count 24 t:LUT5
+select -assert-count 11 t:LUT4
+select -assert-count 25 t:LUT5
 select -assert-count 32 t:LUT6
 select -assert-count 128 t:RAM128X1D
 

misc/abc/abc_mux.ys

@@ -2,4 +2,4 @@ read_verilog ../top_mux.v
 proc
 synth -top top
 abc
-select -assert-count 139 t:$_MUX_
+select -assert-count 104 t:$_MUX_

misc/abc/abc_mux4.ys

 read_verilog ../top_mux.v
 synth -top top
 abc -mux4
-select -assert-count 75 t:$_MUX4_
+select -assert-count 61 t:$_MUX4_

misc/abc/abc_mux_cmos3.ys

@@ -2,5 +2,5 @@ read_verilog ../top_mux.v
 synth -top top
 tee -o result.out abc -g cmos3
  abc -g cmos3
-select -assert-count 144 t:$_AOI3_
-select -assert-count 169 t:$_OAI3_
+select -assert-count 153 t:$_AOI3_
+select -assert-count 168 t:$_OAI3_

misc/abc/abc_mux_cmos4.ys

@@ -3,7 +3,7 @@ synth -top top
 tee -o result.out abc -g cmos4
  abc -g cmos4
 
-select -assert-count 111 t:$_AOI3_
-select -assert-count 28  t:$_AOI4_
-select -assert-count 111 t:$_AOI3_
-select -assert-count 24  t:$_OAI4_
+select -assert-count 80 t:$_AOI3_
+select -assert-count 21  t:$_AOI4_
+select -assert-count 118 t:$_OAI3_
+select -assert-count 46  t:$_OAI4_

regression/issue_01372/issue_01372.ys

@@ -3,5 +3,5 @@ read -formal ../top.v
 prep -top mcvesix
 tee -o result.log equiv_opt -assert prep # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mcvesix # Constrain all select calls below inside the top module
-select -assert-count 2 w:k s:32
+#cd mcvesix # Constrain all select calls below inside the top module
+#select -assert-count 2 w:k s:32