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lvzhengyang
yosys-tests
Commits
c4d6a250
Commit
c4d6a250
authored
Feb 06, 2020
by
Miodrag Milanovic
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Test fixes
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eaf24f84
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9 changed files
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25 additions
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24 deletions
+25
-24
architecture/synth_ecp5/synth_ecp5_nobram.ys
+3
-2
architecture/synth_ice40/synth_ice40_nobram.ys
+2
-2
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys
+8
-8
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys
+2
-2
misc/abc/abc_mux.ys
+1
-1
misc/abc/abc_mux4.ys
+1
-1
misc/abc/abc_mux_cmos3.ys
+2
-2
misc/abc/abc_mux_cmos4.ys
+4
-4
regression/issue_01372/issue_01372.ys
+2
-2
No files found.
architecture/synth_ecp5/synth_ecp5_nobram.ys
View file @
c4d6a250
...
...
@@ -34,8 +34,9 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 144 t:LUT4
select -assert-count 17 t:PFUMX
stat
select -assert-count 143 t:LUT4
select -assert-count 16 t:PFUMX
select -assert-count 32 t:TRELLIS_DPR16X4
select -assert-count 143 t:TRELLIS_FF
select -assert-none t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
architecture/synth_ice40/synth_ice40_nobram.ys
View file @
c4d6a250
...
...
@@ -30,8 +30,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
stat
select -assert-count 6 t:SB_DFF
select -assert-count 384 t:SB_DFFE
select -assert-count 37
6
t:SB_LUT4
select -assert-count 37
2
t:SB_LUT4
select -assert-none t:SB_DFF t:SB_DFFE t:SB_LUT4 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys
View file @
c4d6a250
...
...
@@ -17,13 +17,13 @@ stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 200 t:FDRE
select -assert-count 2
6
t:LUT1
select -assert-count
16
t:LUT2
select -assert-count 4
9
t:LUT3
select -assert-count
5
t:LUT4
select -assert-count 1
00
t:LUT5
select -assert-count 2
84
t:LUT6
select -assert-count 3
41
t:MUXF7
select -assert-count 1
54
t:MUXF8
select -assert-count 2
7
t:LUT1
select -assert-count
23
t:LUT2
select -assert-count 4
8
t:LUT3
select -assert-count
24
t:LUT4
select -assert-count 1
38
t:LUT5
select -assert-count 2
27
t:LUT6
select -assert-count 3
18
t:MUXF7
select -assert-count 1
42
t:MUXF8
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys
View file @
c4d6a250
...
...
@@ -20,8 +20,8 @@ select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 5 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 1
2
t:LUT4
select -assert-count 2
4
t:LUT5
select -assert-count 1
1
t:LUT4
select -assert-count 2
5
t:LUT5
select -assert-count 32 t:LUT6
select -assert-count 128 t:RAM128X1D
...
...
misc/abc/abc_mux.ys
View file @
c4d6a250
...
...
@@ -2,4 +2,4 @@ read_verilog ../top_mux.v
proc
synth -top top
abc
select -assert-count 1
39
t:$_MUX_
select -assert-count 1
04
t:$_MUX_
misc/abc/abc_mux4.ys
View file @
c4d6a250
read_verilog ../top_mux.v
synth -top top
abc -mux4
select -assert-count
75
t:$_MUX4_
select -assert-count
61
t:$_MUX4_
misc/abc/abc_mux_cmos3.ys
View file @
c4d6a250
...
...
@@ -2,5 +2,5 @@ read_verilog ../top_mux.v
synth -top top
tee -o result.out abc -g cmos3
abc -g cmos3
select -assert-count 1
44
t:$_AOI3_
select -assert-count 16
9
t:$_OAI3_
select -assert-count 1
53
t:$_AOI3_
select -assert-count 16
8
t:$_OAI3_
misc/abc/abc_mux_cmos4.ys
View file @
c4d6a250
...
...
@@ -3,7 +3,7 @@ synth -top top
tee -o result.out abc -g cmos4
abc -g cmos4
select -assert-count
111
t:$_AOI3_
select -assert-count 2
8
t:$_AOI4_
select -assert-count 11
1 t:$_AO
I3_
select -assert-count
24
t:$_OAI4_
select -assert-count
80
t:$_AOI3_
select -assert-count 2
1
t:$_AOI4_
select -assert-count 11
8 t:$_OA
I3_
select -assert-count
46
t:$_OAI4_
regression/issue_01372/issue_01372.ys
View file @
c4d6a250
...
...
@@ -3,5 +3,5 @@ read -formal ../top.v
prep -top mcvesix
tee -o result.log equiv_opt -assert prep # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mcvesix # Constrain all select calls below inside the top module
select -assert-count 2 w:k s:32
#
cd mcvesix # Constrain all select calls below inside the top module
#
select -assert-count 2 w:k s:32
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