Commit c4152912 by Eddie Hung

Add missing reset input, FIXME on test7, rename

parent adf1f69e
...@@ -68,6 +68,8 @@ elif [ "$1" = "synth_xilinx_srl" ]; then ...@@ -68,6 +68,8 @@ elif [ "$1" = "synth_xilinx_srl" ]; then
iverilog -DTEST8 synth8.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v iverilog -DTEST8 synth8.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run run
iverilog -DTEST9 synth9.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v iverilog -DTEST9 synth9.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
#run
#iverilog -DTEST10 synth10.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif [ "$1" = "synth_greenpak4" ]; then elif [ "$1" = "synth_greenpak4" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
else else
......
...@@ -15,3 +15,5 @@ design -reset ...@@ -15,3 +15,5 @@ design -reset
script ../test8.ys script ../test8.ys
design -reset design -reset
script ../test9.ys script ../test9.ys
design -reset
script ../test10.ys
...@@ -5,5 +5,5 @@ clean -purge ...@@ -5,5 +5,5 @@ clean -purge
write_verilog synth7.v write_verilog synth7.v
# Check that shift registers with resets are not inferred into SRLs # Check that shift registers with resets are not inferred into SRLs
cd $paramod\template\depth=131\er_is_reset=1; select t:SRL* -assert-count 0 cd $paramod\shift_reg\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
cd $paramod\template\inferred=1\init=1\neg_clk=1\depth=131\er_is_reset=1; select t:SRL* -assert-count 0 cd $paramod\shift_reg\inferred=1\init=1\neg_clk=1\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
...@@ -5,4 +5,4 @@ clean -purge ...@@ -5,4 +5,4 @@ clean -purge
write_verilog synth8.v write_verilog synth8.v
# Check that wide shift registers are not a problem # Check that wide shift registers are not a problem
cd $paramod\template\width=131\depth=131; select t:FD* -assert-count 0 cd $paramod\shift_reg\width=131\depth=131; select t:FD* -assert-count 0
...@@ -5,4 +5,4 @@ clean -purge ...@@ -5,4 +5,4 @@ clean -purge
write_verilog synth9.v write_verilog synth9.v
# Check that wide shift registers are not a problem # Check that wide shift registers are not a problem
cd $paramod\template\width=131\inferred=1\init=1\neg_clk=1\depth=131; select t:FD* -assert-count 0 cd $paramod\shift_reg\width=131\inferred=1\init=1\neg_clk=1\depth=131; select t:FD* -assert-count 0
...@@ -17,7 +17,7 @@ module testbench; ...@@ -17,7 +17,7 @@ module testbench;
end end
reg [`N-1:0] a; reg [`N-1:0] a;
reg e; reg e, r;
wire [`N-1:0] y; wire [`N-1:0] y;
wire [`N-1:0] z; wire [`N-1:0] z;
...@@ -25,6 +25,7 @@ module testbench; ...@@ -25,6 +25,7 @@ module testbench;
.clk (clk ), .clk (clk ),
.a (a), .a (a),
.e (e), .e (e),
.r (r),
.z (y) .z (y)
); );
...@@ -32,11 +33,14 @@ module testbench; ...@@ -32,11 +33,14 @@ module testbench;
.clk (clk ), .clk (clk ),
.a (a), .a (a),
.e (e), .e (e),
.r (r),
.z (z) .z (z)
); );
always @(negedge clk) always @(negedge clk) begin
e <= $random; e <= $random;
r <= $random;
end
generate generate
genvar i; genvar i;
......
...@@ -5,47 +5,48 @@ generate ...@@ -5,47 +5,48 @@ generate
genvar i; genvar i;
`ifdef TEST1 `ifdef TEST1
for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred
template #(.depth(i+1)) sr(clk, a[i], 1'b1, z[i]); shift_reg #(.depth(i+1)) sr(clk, a[i], 1'b1, z[i]);
end end
`elsif TEST2 `elsif TEST2
for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_not_inferred for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_not_inferred
template #(.depth(i+1)) sr(clk, a[i], e, z[i]); shift_reg #(.depth(i+1)) sr(clk, a[i], e, z[i]);
end end
`elsif TEST3 `elsif TEST3
for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_with_init_inferred for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_with_init_inferred
template #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, z[i]); shift_reg #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, z[i]);
end end
`elsif TEST4 `elsif TEST4
for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_not_inferred for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_not_inferred
template #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, z[i]); shift_reg #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, z[i]);
end end
`elsif TEST5 `elsif TEST5
for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_inferred for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_inferred
template #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, z[i]); shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, z[i]);
end end
`elsif TEST6 `elsif TEST6
for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
template #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, z[i]); shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, z[i]);
end end
`elsif TEST7 `elsif TEST7
// Check that use of resets block shreg // Check that use of resets block shreg
(* keep *) (* keep *)
template #(.depth(`N), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[0], r, z[0]); shift_reg #(.depth(`N), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[1], r, z[0]);
(* keep *) (* keep *)
template #(.depth(`N), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[1], r, z[1]); shift_reg #(.depth(`N), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[2], r, FIXME /*z[1]*/);
assign z[`N-1:2] = 'b0; // Suppress no driver warning assign z[`N-1:2] = 'b0; // Suppress no driver warning
`elsif TEST8 `elsif TEST8
// Check multi-bit works // Check multi-bit works
(* keep *) (* keep *)
template #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, z); shift_reg #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, z);
`elsif TEST9 `elsif TEST9
(* keep *) (* keep *)
template #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, z); shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, z);
`elsif TEST10
`endif `endif
endgenerate endgenerate
endmodule endmodule
module template #(parameter width=1) (input clk, input [width-1:0] a, input er, output [width-1:0] z); module shift_reg #(parameter width=1) (input clk, input [width-1:0] a, input er, output [width-1:0] z);
parameter inferred = 0; parameter inferred = 0;
parameter init = 0; parameter init = 0;
parameter neg_clk = 0; parameter neg_clk = 0;
......
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