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lvzhengyang
yosys-tests
Commits
c4152912
Commit
c4152912
authored
Mar 15, 2019
by
Eddie Hung
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Add missing reset input, FIXME on test7, rename
parent
adf1f69e
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9 changed files
with
286 additions
and
277 deletions
+286
-277
architecture/run.sh
+2
-0
architecture/scripts/synth_xilinx_srl.ys
+2
-0
architecture/synth_xilinx_srl/test1.ys
+130
-130
architecture/synth_xilinx_srl/test6.ys
+130
-130
architecture/synth_xilinx_srl/test7.ys
+2
-2
architecture/synth_xilinx_srl/test8.ys
+1
-1
architecture/synth_xilinx_srl/test9.ys
+1
-1
architecture/synth_xilinx_srl/testbench.v
+6
-2
architecture/synth_xilinx_srl/top.v
+12
-11
No files found.
architecture/run.sh
View file @
c4152912
...
...
@@ -68,6 +68,8 @@ elif [ "$1" = "synth_xilinx_srl" ]; then
iverilog
-DTEST8
synth8.v
-o
testbench ../testbench.v
-I
.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
run
iverilog
-DTEST9
synth9.v
-o
testbench ../testbench.v
-I
.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
#run
#iverilog -DTEST10 synth10.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif
[
"
$1
"
=
"synth_greenpak4"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
else
...
...
architecture/scripts/synth_xilinx_srl.ys
View file @
c4152912
...
...
@@ -15,3 +15,5 @@ design -reset
script ../test8.ys
design -reset
script ../test9.ys
design -reset
script ../test10.ys
architecture/synth_xilinx_srl/test1.ys
View file @
c4152912
...
...
@@ -4,134 +4,134 @@ rename -top synth
clean -purge
write_verilog synth1.v
cd $paramod\
template
\depth=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=2; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=3; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=4; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=5; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=6; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=7; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=8; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=9; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=10; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=11; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=12; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=13; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=14; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=15; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=16; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=17; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=18; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=19; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=20; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=21; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=22; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=23; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=24; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=25; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=26; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=27; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=28; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=29; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=30; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=31; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=32; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=33; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=34; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=35; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=36; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=37; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=38; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=39; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=40; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=41; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=42; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=43; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=44; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=45; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=46; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=47; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=48; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=49; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=50; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=51; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=52; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=53; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=54; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=55; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=56; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=57; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=58; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=59; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=60; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=61; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=62; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=63; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=64; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=65; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=66; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=67; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=68; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=69; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=70; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=71; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=72; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=73; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=74; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=75; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=76; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=77; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=78; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=79; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=80; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=81; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=82; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=83; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=84; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=85; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=86; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=87; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=88; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=89; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=90; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=91; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=92; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=93; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=94; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=95; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=96; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=97; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=98; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=99; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=100; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=101; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=102; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=103; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=104; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=105; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=106; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=107; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=108; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=109; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=110; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=111; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=112; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=113; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=114; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=115; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=116; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=117; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=118; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=119; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=120; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=121; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=122; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=123; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=124; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=125; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=126; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=127; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=128; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=129; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\depth=130; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=2; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=3; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=4; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=5; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=6; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=7; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=8; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=9; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=10; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=11; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=12; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=13; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=14; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=15; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=16; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=17; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=18; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=19; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=20; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=21; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=22; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=23; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=24; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=25; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=26; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=27; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=28; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=29; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=30; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=31; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=32; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=33; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=34; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=35; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=36; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=37; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=38; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=39; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=40; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=41; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=42; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=43; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=44; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=45; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=46; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=47; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=48; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=49; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=50; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=51; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=52; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=53; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=54; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=55; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=56; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=57; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=58; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=59; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=60; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=61; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=62; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=63; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=64; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=65; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=66; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=67; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=68; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=69; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=70; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=71; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=72; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=73; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=74; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=75; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=76; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=77; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=78; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=79; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=80; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=81; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=82; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=83; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=84; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=85; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=86; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=87; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=88; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=89; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=90; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=91; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=92; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=93; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=94; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=95; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=96; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=97; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=98; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=99; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=100; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=101; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=102; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=103; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=104; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=105; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=106; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=107; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=108; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=109; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=110; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=111; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=112; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=113; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=114; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=115; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=116; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=117; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=118; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=119; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=120; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=121; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=122; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=123; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=124; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=125; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=126; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=127; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=128; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=129; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\depth=130; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
architecture/synth_xilinx_srl/test6.ys
View file @
c4152912
...
...
@@ -4,133 +4,133 @@ rename -top synth
clean -purge
write_verilog synth6.v
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=2; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=3; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=4; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=5; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=6; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=7; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=8; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=9; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=10; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=11; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=12; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=13; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=14; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=15; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=16; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=17; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=18; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=19; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=20; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=21; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=22; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=23; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=24; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=25; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=26; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=27; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=28; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=29; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=30; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=31; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=32; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=33; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=34; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=35; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=36; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=37; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=38; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=39; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=40; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=41; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=42; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=43; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=44; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=45; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=46; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=47; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=48; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=49; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=50; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=51; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=52; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=53; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=54; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=55; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=56; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=57; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=58; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=59; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=60; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=61; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=62; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=63; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=64; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=65; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=66; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=67; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=68; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=69; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=70; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=71; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=72; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=73; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=74; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=75; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=76; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=77; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=78; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=79; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=80; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=81; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=82; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=83; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=84; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=85; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=86; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=87; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=88; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=89; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=90; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=91; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=92; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=93; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=94; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=95; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=96; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=97; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=98; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=99; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=100; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=101; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=102; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=103; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=104; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=105; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=106; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=107; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=108; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=109; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=110; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=111; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=112; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=113; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=114; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=115; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=116; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=117; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=118; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=119; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=120; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=121; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=122; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=123; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=124; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=125; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=126; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=127; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=128; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=129; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=130; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=1; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=2; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=3; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=4; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=5; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=6; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=7; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=8; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=9; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=10; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=11; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=12; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=13; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=14; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=15; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=16; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=17; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=18; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=19; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=20; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=21; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=22; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=23; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=24; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=25; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=26; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=27; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=28; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=29; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=30; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=31; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=32; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=33; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=34; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=35; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=36; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=37; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=38; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=39; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=40; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=41; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=42; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=43; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=44; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=45; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=46; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=47; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=48; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=49; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=50; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=51; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=52; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=53; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=54; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=55; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=56; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=57; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=58; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=59; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=60; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=61; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=62; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=63; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=64; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=65; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=66; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=67; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=68; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=69; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=70; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=71; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=72; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=73; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=74; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=75; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=76; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=77; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=78; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=79; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=80; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=81; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=82; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=83; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=84; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=85; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=86; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=87; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=88; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=89; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=90; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=91; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=92; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=93; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=94; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=95; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=96; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=97; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=98; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=99; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=100; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=101; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=102; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=103; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=104; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=105; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=106; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=107; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=108; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=109; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=110; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=111; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=112; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=113; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=114; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=115; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=116; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=117; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=118; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=119; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=120; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=121; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=122; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=123; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=124; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=125; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=126; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=127; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=128; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=129; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=130; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% t:* %n %i -assert-none
architecture/synth_xilinx_srl/test7.ys
View file @
c4152912
...
...
@@ -5,5 +5,5 @@ clean -purge
write_verilog synth7.v
# Check that shift registers with resets are not inferred into SRLs
cd $paramod\
template
\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
cd $paramod\
template
\inferred=1\init=1\neg_clk=1\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
cd $paramod\
shift_reg
\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
cd $paramod\
shift_reg
\inferred=1\init=1\neg_clk=1\depth=131\er_is_reset=1; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/test8.ys
View file @
c4152912
...
...
@@ -5,4 +5,4 @@ clean -purge
write_verilog synth8.v
# Check that wide shift registers are not a problem
cd $paramod\
template
\width=131\depth=131; select t:FD* -assert-count 0
cd $paramod\
shift_reg
\width=131\depth=131; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/test9.ys
View file @
c4152912
...
...
@@ -5,4 +5,4 @@ clean -purge
write_verilog synth9.v
# Check that wide shift registers are not a problem
cd $paramod\
template
\width=131\inferred=1\init=1\neg_clk=1\depth=131; select t:FD* -assert-count 0
cd $paramod\
shift_reg
\width=131\inferred=1\init=1\neg_clk=1\depth=131; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/testbench.v
View file @
c4152912
...
...
@@ -17,7 +17,7 @@ module testbench;
end
reg
[
`N
-
1
:
0
]
a
;
reg
e
;
reg
e
,
r
;
wire
[
`N
-
1
:
0
]
y
;
wire
[
`N
-
1
:
0
]
z
;
...
...
@@ -25,6 +25,7 @@ module testbench;
.
clk
(
clk
)
,
.
a
(
a
)
,
.
e
(
e
)
,
.
r
(
r
)
,
.
z
(
y
)
)
;
...
...
@@ -32,11 +33,14 @@ module testbench;
.
clk
(
clk
)
,
.
a
(
a
)
,
.
e
(
e
)
,
.
r
(
r
)
,
.
z
(
z
)
)
;
always
@
(
negedge
clk
)
always
@
(
negedge
clk
)
begin
e
<=
$
random
;
r
<=
$
random
;
end
generate
genvar
i
;
...
...
architecture/synth_xilinx_srl/top.v
View file @
c4152912
...
...
@@ -5,47 +5,48 @@ generate
genvar
i
;
`ifdef
TEST1
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
pos_clk_no_enable_no_init_not_inferred
template
#(
.
depth
(
i
+
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
z
[
i
])
;
end
`elsif
TEST2
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
pos_clk_with_enable_no_init_not_inferred
template
#(
.
depth
(
i
+
1
))
sr
(
clk
,
a
[
i
]
,
e
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
))
sr
(
clk
,
a
[
i
]
,
e
,
z
[
i
])
;
end
`elsif
TEST3
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
pos_clk_with_enable_with_init_inferred
template
#(
.
depth
(
i
+
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
sr
(
clk
,
a
[
i
]
,
e
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
sr
(
clk
,
a
[
i
]
,
e
,
z
[
i
])
;
end
`elsif
TEST4
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
neg_clk_no_enable_no_init_not_inferred
template
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
z
[
i
])
;
end
`elsif
TEST5
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
neg_clk_no_enable_no_init_inferred
template
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
))
sr
(
clk
,
a
[
i
]
,
1'b1
,
z
[
i
])
;
end
`elsif
TEST6
for
(
i
=
0
;
i
<
`N
;
i
=
i
+
1
)
begin
:
neg_clk_with_enable_with_init_inferred
template
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
sr
(
clk
,
a
[
i
]
,
e
,
z
[
i
])
;
shift_reg
#(
.
depth
(
i
+
1
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
sr
(
clk
,
a
[
i
]
,
e
,
z
[
i
])
;
end
`elsif
TEST7
// Check that use of resets block shreg
(
*
keep
*
)
template
#(
.
depth
(
`N
)
,
.
er_is_reset
(
1
))
pos_clk_no_enable_no_init_not_inferred_with_reset
(
clk
,
a
[
0
]
,
r
,
z
[
0
])
;
shift_reg
#(
.
depth
(
`N
)
,
.
er_is_reset
(
1
))
pos_clk_no_enable_no_init_not_inferred_with_reset
(
clk
,
a
[
1
]
,
r
,
z
[
0
])
;
(
*
keep
*
)
template
#(
.
depth
(
`N
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
)
,
.
er_is_reset
(
1
))
neg_clk_no_enable_with_init_with_inferred_with_reset
(
clk
,
a
[
1
]
,
r
,
z
[
1
]
)
;
shift_reg
#(
.
depth
(
`N
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
)
,
.
er_is_reset
(
1
))
neg_clk_no_enable_with_init_with_inferred_with_reset
(
clk
,
a
[
2
]
,
r
,
FIXME
/*z[1]*/
)
;
assign
z
[
`N
-
1
:
2
]
=
'b0
;
// Suppress no driver warning
`elsif
TEST8
// Check multi-bit works
(
*
keep
*
)
template
#(
.
depth
(
`N
)
,
.
width
(
`N
))
pos_clk_no_enable_no_init_not_inferred_N_width
(
clk
,
a
,
r
,
z
)
;
shift_reg
#(
.
depth
(
`N
)
,
.
width
(
`N
))
pos_clk_no_enable_no_init_not_inferred_N_width
(
clk
,
a
,
r
,
z
)
;
`elsif
TEST9
(
*
keep
*
)
template
#(
.
depth
(
`N
)
,
.
width
(
`N
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
neg_clk_no_enable_with_init_with_inferred_N_width
(
clk
,
a
,
r
,
z
)
;
shift_reg
#(
.
depth
(
`N
)
,
.
width
(
`N
)
,
.
neg_clk
(
1
)
,
.
inferred
(
1
)
,
.
init
(
1
))
neg_clk_no_enable_with_init_with_inferred_N_width
(
clk
,
a
,
r
,
z
)
;
`elsif
TEST10
`endif
endgenerate
endmodule
module
template
#(
parameter
width
=
1
)
(
input
clk
,
input
[
width
-
1
:
0
]
a
,
input
er
,
output
[
width
-
1
:
0
]
z
)
;
module
shift_reg
#(
parameter
width
=
1
)
(
input
clk
,
input
[
width
-
1
:
0
]
a
,
input
er
,
output
[
width
-
1
:
0
]
z
)
;
parameter
inferred
=
0
;
parameter
init
=
0
;
parameter
neg_clk
=
0
;
...
...
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