More tests

architecture/synth_xilinx_srl/run-test.sh

@@ -20,4 +20,9 @@ fi
 wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
 python3 generate_lfsr.py
 python3 generate.py
-${MAKE:-make} -f ../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../techlibs/xilinx/cells_sim.v"
+${MAKE:-make} -f ../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../techlibs/xilinx/cells_sim.v"
+${MAKE:-make} -f ../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx -retime' -l ../../../../techlibs/xilinx/cells_sim.v"
+
+for ys in *.ys; do
+    yosys -q $ys
+done

architecture/synth_xilinx_srl/test21.ys

-read_verilog -icells -DTEST21 ../top.v
-synth_xilinx -retime -flatten
-rename -top synth
-clean -purge
-write_verilog synth21.v
-
 # Check that retiming does not infer shift registers
-select t:SRL* -assert-count 0
-select t:FD* -assert-min 20
+design -reset; read_verilog test21a.out/test21a_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20
+design -reset; read_verilog test21b.out/test21b_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20

architecture/synth_xilinx_srl/test22.ys

-read_verilog -icells -DTEST22 ../top.v
-synth_xilinx -retime -flatten
-rename -top synth
-clean -purge
-write_verilog synth22.v
-
-# Check that retiming can still infer shift registers
-select t:SRL* -assert-min 1
-select t:FD* -assert-min 16