Update tests

architecture/synth_xilinx_srl/run-test.sh

@@ -17,7 +17,7 @@ if ! which iverilog > /dev/null ; then
   exit 1
 fi
 
-#wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
-#python3 generate_lfsr.py
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
+python3 generate_lfsr.py
 python3 generate.py
 ${MAKE:-make} -f ../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../techlibs/xilinx/cells_sim.v"

architecture/synth_xilinx_srl/test13.ys

-read_verilog -icells -DTEST13 ../top.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth13.v
-
 # Check that non chain users block SRLs
-cd synth; cd sr_fixed_length_other_users_port; select t:SRL* -assert-count 0
-cd synth; cd sr_var_length_other_users_port; select t:SRL* -assert-count 0
-cd synth; cd sr_fixed_length_other_users_xor; select t:SRL* -assert-count 0
-cd synth; cd sr_var_length_other_users_xor; select t:SRL* -assert-count 0
+design -reset; read_verilog test13a.out/test13a_syn0.v; select t:SRL* -assert-count 0
+design -reset; read_verilog test13b.out/test13b_syn0.v; select t:SRL* -assert-count 0
+design -reset; read_verilog test13c.out/test13c_syn0.v; select t:SRL* -assert-count 0
+design -reset; read_verilog test13d.out/test13d_syn0.v; select t:SRL* -assert-count 0

architecture/synth_xilinx_srl/test14.ys

-read_verilog -icells -DTEST14 ../top.v
-read_verilog ../ug901.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth14.v
-
-cd synth; cd sr0; select t:SRLC32E -assert-count 1
-cd synth; cd sr1; select t:SRLC32E -assert-count 1
-cd synth; cd sr2; select t:SRLC32E -assert-count 1

architecture/synth_xilinx_srl/test2.ys

-read_verilog -icells -DTEST2 ../top.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth2.v

architecture/synth_xilinx_srl/test20.ys

-read_verilog -icells -DTEST20 ../top.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth20.v
-
-# Check that wide shift registers are not a problem
-cd synth; cd neg_clk_no_enable_with_init_with_inferred2_N_width; select t:FD* -assert-count 0
+design -reset; read_verilog test20.out/test20_syn0.v; select t:FD* -assert-count 0

architecture/synth_xilinx_srl/test3.ys

-read_verilog -icells -DTEST3 ../top.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth3.v

architecture/synth_xilinx_srl/test4.ys

-read_verilog -icells -DTEST4 ../top.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth4.v

architecture/synth_xilinx_srl/test5.ys

-read_verilog -icells -DTEST5 ../top.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth5.v

architecture/synth_xilinx_srl/test7.ys

-read_verilog -icells -DTEST7 ../top.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth7.v
-
 # Check that shift registers with resets are not inferred into SRLs
-cd synth; cd pos_clk_no_enable_no_init_not_inferred_with_reset; select t:SRL* -assert-count 0
-cd synth; cd neg_clk_no_enable_with_init_with_inferred_with_reset; select t:SRL* -assert-count 0
-cd synth; cd pos_clk_no_enable_no_init_not_inferred_with_reset_var_len; select t:SRL* -assert-count 0
-cd synth; cd neg_clk_no_enable_with_init_with_inferred_with_reset_var_len; select t:SRL* -assert-count 0
+design -reset; read_verilog test7a.out/test7a_syn0.v; select t:SRL* -assert-count 0
+design -reset; read_verilog test7b.out/test7b_syn0.v; select t:SRL* -assert-count 0
+design -reset; read_verilog test7c.out/test7c_syn0.v; select t:SRL* -assert-count 0
+design -reset; read_verilog test7d.out/test7d_syn0.v; select t:SRL* -assert-count 0

architecture/synth_xilinx_srl/test8.ys

-read_verilog -icells -DTEST8 ../top.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth8.v
-
 # Check that wide shift registers are not a problem
-cd synth; cd pos_clk_no_enable_no_init_not_inferred_N_width; select t:FD* -assert-count 0
+read_verilog test8.out/test8_syn0.v; select t:FD* -assert-count 0

architecture/synth_xilinx_srl/test9.ys

-read_verilog -icells -DTEST9 ../top.v
-synth_xilinx
-rename -top synth
-clean -purge
-write_verilog synth9.v
-
-# Check that wide shift registers are not a problem
-cd synth; cd neg_clk_no_enable_with_init_with_inferred_N_width; select t:FD* -assert-count 0
+read_verilog test9.out/test9_syn0.v; select t:FD* -assert-count 0

architecture/synth_xilinx_srl/ug901.ys

+design -reset; read_verilog ug901a.out/ug901a_syn0.v; select t:SRLC32E -assert-count 1
+design -reset; read_verilog ug901b.out/ug901b_syn0.v; select t:SRLC32E -assert-count 1
+design -reset; read_verilog ug901c.out/ug901c_syn0.v; select t:SRLC32E -assert-count 1