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yosys-tests
Commit af072aec by Eddie Hung
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Cleanup and add a comment

parent 7664abcf
Showing with 2 additions and 1 deletions
architecture/synth_xilinx_dsp/assert_area.py
...@@ -34,6 +34,7 @@ for fn in glob.glob('*.v'): ...@@ -34,6 +34,7 @@ for fn in glob.glob('*.v'):
count_DFF = 0 count_DFF = 0
if Preg: if Preg:
count_DFF += A + B count_DFF += A + B
# TODO: Assert on number of FD* too
# TODO: Assert on number of CARRY4s too # TODO: Assert on number of CARRY4s too
bn,_ = os.path.splitext(fn) bn,_ = os.path.splitext(fn)
......
architecture/synth_xilinx_dsp/run-test.sh
...@@ -22,7 +22,7 @@ fi ...@@ -22,7 +22,7 @@ fi
cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
python3 ../assert_area.py python3 ../assert_area.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *__.v EXTRA_FLAGS="\ ${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
-p 'design -copy-to __test __test; \ -p 'design -copy-to __test __test; \
synth_xilinx; \ synth_xilinx; \
design -copy-from __test *; \ design -copy-from __test *; \
......
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