Cleanup and add a comment

architecture/synth_xilinx_dsp/assert_area.py

@@ -34,6 +34,7 @@ for fn in glob.glob('*.v'):
     count_DFF = 0
     if Preg:
         count_DFF += A + B
+    # TODO: Assert on number of FD* too
     # TODO: Assert on number of CARRY4s too
 
     bn,_ = os.path.splitext(fn)

architecture/synth_xilinx_dsp/run-test.sh

@@ -22,7 +22,7 @@ fi
 cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
 PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
 python3 ../assert_area.py
-${MAKE:-make} -f ../../../../tools/autotest.mk $seed *__.v EXTRA_FLAGS="\
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
     -p 'design -copy-to __test __test; \
         synth_xilinx; \
         design -copy-from __test *; \