Fix tests due to text change or QoR

architecture/synth_anlogic/anlogic_determine_init_eqn.ys

@@ -12,7 +12,6 @@ opt -fast -mux_undef -undriven -fine
 memory_map
 opt -undriven -fine
 techmap -map +/techmap.v -map +/anlogic/arith_map.v
-dffsr2dff
 techmap -D NO_LUT -map +/anlogic/cells_map.v
 dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit
 opt_expr -mux_undef

architecture/synth_ecp5/ecp5_ffinit.ys

@@ -11,7 +11,7 @@ opt -fast -mux_undef -undriven -fine
 techmap -map +/techmap.v -map +/ecp5/arith_map.v
 abc -dff
 opt -fast -mux_undef -undriven -fine
-dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
+dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*
 techmap -D NO_LUT -map +/ecp5/cells_map.v
 opt_expr -mux_undef
 simplemap

backends/write_intersynth/write_intersynth_cant_export_fail.pat

-ERROR: Can't export composite or non-word-wide signal { \\y \\A }.
+ERROR: Can't export composite or non-word-wide signal

misc/abc/abc_g_cmos.ys

@@ -5,4 +5,4 @@ abc -g cmos
 select -assert-count 1 t:$_NAND_
 select -assert-count 1 t:$_NOT_
 select -assert-count 1 t:$_OAI3_
-select -assert-count 2 t:$_XNOR_
+select -assert-count 1 t:$_XNOR_

misc/abc/abc_mux.ys

@@ -2,4 +2,4 @@ read_verilog ../top_mux.v
 proc
 synth -top top
 abc
-select -assert-count 109 t:$_MUX_
+select -assert-count 139 t:$_MUX_

misc/abc/abc_mux4.ys

 read_verilog ../top_mux.v
 synth -top top
 abc -mux4
-select -assert-count 60 t:$_MUX4_
+select -assert-count 75 t:$_MUX4_

misc/abc/abc_mux_cmos3.ys

@@ -2,5 +2,5 @@ read_verilog ../top_mux.v
 synth -top top
 tee -o result.out abc -g cmos3
  abc -g cmos3
-select -assert-count 121 t:$_AOI3_
-select -assert-count 163 t:$_OAI3_
+select -assert-count 144 t:$_AOI3_
+select -assert-count 169 t:$_OAI3_

misc/abc/abc_mux_cmos4.ys

@@ -3,7 +3,7 @@ synth -top top
 tee -o result.out abc -g cmos4
  abc -g cmos4
 
-select -assert-count 90 t:$_AOI3_
-select -assert-count 17  t:$_AOI4_
-select -assert-count 132 t:$_OAI3_
-select -assert-count 37  t:$_OAI4_
+select -assert-count 111 t:$_AOI3_
+select -assert-count 28  t:$_AOI4_
+select -assert-count 111 t:$_OAI3_
+select -assert-count 24  t:$_OAI4_

misc/select/select_set_with_assert_any_fail.pat

-ERROR: Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.
+ERROR: Option -set can not be combined with 

misc/select/select_set_with_assert_max_fail.pat

-ERROR: Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.
+ERROR: Option -set can not be combined with 

misc/select/select_set_with_count_fail.pat

-ERROR: Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.
+ERROR: Option -set can not be combined with 

misc/select/select_set_with_del_fail.pat

-ERROR: Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.
+ERROR: Option -set can not be combined with 

misc/select/select_set_with_list_fail.pat

-ERROR: Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.
+ERROR: Option -set can not be combined with 

misc/setundef/setundef_one_of_options_fail.pat

-ERROR: One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified.
+ERROR: One of the options 

regression/issue_00082/issue_00082.ys

-logger -expect error "no AST_WIRE node" 1
+logger -expect error "task/function argument direction missing" 1
 read_verilog top.v

simple/dffsr2dff/dffsr2dff.ys

-read_verilog ../top.v
-proc
-dffsr2dff
-techmap
-dffsr2dff
-design -reset
-read_verilog ../top.v
-synth -top top
-dffsr2dff
-flatten
-opt
-opt_rmdff
-dffsr2dff
-

simple/dffsr2dff/top.v

-module dffsr
-    ( input d, clk, pre, clr, output reg q );
-	always @( posedge clk, posedge pre, negedge clr )
-		if ( pre )
-			q <= 1'b1;
-		else if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module top (
-input clk,
-input a,
-output b
-);
-
-dffsr u_dffsr (
-        .clk (clk ),
-        .clr (1'b1),
-        .pre (1'b1),
-        .d (a ),
-        .q (b )
-    );
-
-endmodule