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yosys-tests
Unverified Commit a7464350 by Miodrag Milanović Committed by GitHub
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Merge pull request #48 from whitequark/add-proc_prune 

Add proc_prune before explicit proc_init
parents 3cd49561 c0788975
Showing with 6 additions and 1 deletions
backends/scripts/write_btor.ys
...@@ -8,6 +8,7 @@ synth -top top ...@@ -8,6 +8,7 @@ synth -top top
write_btor btor1.btor write_btor btor1.btor
design -reset design -reset
read_verilog -sv ../top.v read_verilog -sv ../top.v
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
......
backends/scripts/write_btor_s.ys
...@@ -7,6 +7,7 @@ synth -top top ...@@ -7,6 +7,7 @@ synth -top top
write_btor -s btor1.btor write_btor -s btor1.btor
design -reset design -reset
read_verilog -sv ../top.v read_verilog -sv ../top.v
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
......
backends/scripts/write_btor_v.ys
...@@ -7,6 +7,7 @@ synth -top top ...@@ -7,6 +7,7 @@ synth -top top
write_btor -v btor1.btor write_btor -v btor1.btor
design -reset design -reset
read_verilog -sv ../top.v read_verilog -sv ../top.v
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
...@@ -51,4 +52,4 @@ write_btor -v btor10.btor ...@@ -51,4 +52,4 @@ write_btor -v btor10.btor
design -reset design -reset
read_verilog -sv ../top_clean.v read_verilog -sv ../top_clean.v
synth -top top synth -top top
write_verilog synth.v write_verilog synth.v
regression/scripts/issue_00444.ys
read_verilog -formal ../top.v read_verilog -formal ../top.v
hierarchy hierarchy
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
......
simple/scripts/opt_merge_share_all.ys
read_verilog -formal ../top.v read_verilog -formal ../top.v
hierarchy hierarchy
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
......
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