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yosys-tests
Commit 97ee0d05 by Eddie Hung
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Fix path

parent e45c8c1e
Showing with 5 additions and 3 deletions
architecture/synth_xilinx_srl/run-test.sh
...@@ -20,10 +20,12 @@ fi ...@@ -20,10 +20,12 @@ fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
python3 generate_lfsr.py python3 generate_lfsr.py
python3 generate.py python3 ../generate.py
${MAKE:-make} -f ../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../techlibs/xilinx/cells_sim.v" cp ../*.v .
${MAKE:-make} -f ../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx -retime' -l ../../../../techlibs/xilinx/cells_sim.v" ${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../../techlibs/xilinx/cells_sim.v"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx -retime' -l ../../../../../techlibs/xilinx/cells_sim.v"
cp ../*.ys .
for ys in *.ys; do for ys in *.ys; do
yosys -q $ys yosys -q $ys
done done
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