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lvzhengyang
yosys-tests
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9335a36b
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9335a36b
authored
Aug 21, 2020
by
Miodrag Milanovic
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architecture/synth_intel/synth_intel_cyclonev.ys
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architecture/synth_intel/synth_intel_cyclonev.ys
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9335a36b
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@@ -2,8 +2,8 @@ read_verilog ../top.v
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@@ -2,8 +2,8 @@ read_verilog ../top.v
hierarchy -top top
hierarchy -top top
proc
proc
#-assert option was skipped because of unproven cells
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
#equiv_opt -assert -map +/intel
_alm
/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
equiv_opt -map +/intel/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
equiv_opt -map +/intel
_alm
/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
cd top # Constrain all select calls below inside the top module
stat
stat
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