Commit 9335a36b by Miodrag Milanovic

Fix location

parent 5d1215a2
...@@ -2,8 +2,8 @@ read_verilog ../top.v ...@@ -2,8 +2,8 @@ read_verilog ../top.v
hierarchy -top top hierarchy -top top
proc proc
#-assert option was skipped because of unproven cells #-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check #equiv_opt -assert -map +/intel_alm/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
equiv_opt -map +/intel/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check equiv_opt -map +/intel_alm/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
stat stat
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment