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yosys-tests
Commit 9335a36b by Miodrag Milanovic
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Fix location

parent 5d1215a2
Showing with 2 additions and 2 deletions
architecture/synth_intel/synth_intel_cyclonev.ys
......@@ -2,8 +2,8 @@ read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
equiv_opt -map +/intel/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
#equiv_opt -assert -map +/intel_alm/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
equiv_opt -map +/intel_alm/cyclonev/cells_sim.v synth_intel_alm -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
......
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