some regression fixes

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys

@@ -13,15 +13,13 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 
 design -load postopt
 cd dynpreaddmultadd
-
 #Vivado synthesizes 1 DSP48E1.
 select -assert-count 1 t:BUFG
-select -assert-count 24 t:FDRE
+select -assert-count 16 t:FDRE
 select -assert-count 1 t:DSP48E1
-select -assert-count 8 t:LUT1
-select -assert-count 17 t:LUT2
-select -assert-count 25 t:LUT4
+select -assert-count 32 t:LUT2
+select -assert-count 9 t:LUT3
 select -assert-count 16 t:MUXCY
 select -assert-count 18 t:XORCY
 
-select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT1 t:LUT2 t:LUT4 t:MUXCY t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:LUT3 t:MUXCY t:XORCY %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys

@@ -19,10 +19,10 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 16 t:FDRE
 select -assert-count 1 t:LUT2
-select -assert-count 8 t:LUT3
+select -assert-count 8 t:LUT4
 select -assert-count 36 t:LUT5
 select -assert-count 38 t:LUT6
 select -assert-count 10 t:MUXF7
 select -assert-count 128 t:RAM128X1D
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D

regression/issue_00329/issue_00329.ys

 read_verilog -mem2reg ../top.v
+proc
 write_verilog result.out

regression/issue_01002/issue_01002.pat

-Estimated number of LCs:         87
+Estimated number of LCs:         75