Fix some regressed tests

architecture/synth_gowin/synth_gowin_nodram.ys

@@ -46,7 +46,7 @@ select -assert-count 16 t:IBUF
 select -assert-count 592 t:LUT3
 select -assert-count 987 t:LUT4
 select -assert-count 464 t:MUX2_LUT5
-select -assert-count 185 t:MUX2_LUT6
+select -assert-count 184 t:MUX2_LUT6
 select -assert-count 64 t:MUX2_LUT7
 select -assert-count 8 t:OBUF
 select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:OBUF %% t:* %D

architecture/synth_ice40/synth_ice40_nobram.ys

@@ -33,5 +33,5 @@ cd top
 
 select -assert-count 6 t:SB_DFF
 select -assert-count 384 t:SB_DFFE
-select -assert-count 377 t:SB_LUT4
+select -assert-count 376 t:SB_LUT4
 select -assert-none t:SB_DFF t:SB_DFFE t:SB_LUT4 %% t:* %D

architecture/synth_intel/synth_intel_a10gx.ys → architecture/synth_intel/synth_intel_arria10gx.ys

@@ -2,8 +2,8 @@ read_verilog ../top.v
 hierarchy -top top
 proc
 #-assert option was skipped because of unproven cells
-#equiv_opt -assert -map +/intel/a10gx/cells_sim.v synth_intel -family a10gx # equivalency check
-equiv_opt -map +/intel/a10gx/cells_sim.v synth_intel -family a10gx # equivalency check
+#equiv_opt -assert -map +/intel/arria10gx/cells_sim.v synth_intel -family arria10gx # equivalency check
+equiv_opt -map +/intel/arria10gx/cells_sim.v synth_intel -family arria10gx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat

architecture/synth_intel/synth_intel_cyclone10.ys → architecture/synth_intel/synth_intel_cyclone10lp.ys

@@ -2,8 +2,8 @@ read_verilog ../top.v
 hierarchy -top top
 proc
 #-assert option was skipped because of unproven cells
-#equiv_opt -assert -map +/intel/cyclone10/cells_sim.v synth_intel -family cyclone10 # equivalency check
-equiv_opt -map +/intel/cyclone10/cells_sim.v synth_intel -family cyclone10 # equivalency check
+#equiv_opt -assert -map +/intel/cyclone10lp/cells_sim.v synth_intel -family cyclone10lp # equivalency check
+equiv_opt -map +/intel/cyclone10lp/cells_sim.v synth_intel -family cyclone10lp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat

architecture/synth_xilinx/synth_xilinx_iopad.ys

@@ -9,10 +9,9 @@ cd dff # Constrain all select calls below inside the top module
 stat
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
-select -assert-count 1 t:IBUF
-select -assert-count 1 t:IBUFG
+select -assert-count 2 t:IBUF
 select -assert-count 1 t:OBUF
-select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
 
 design -load read
 hierarchy -top dffe
@@ -23,8 +22,7 @@ cd dffe # Constrain all select calls below inside the top module
 stat
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
-select -assert-count 2 t:IBUF
-select -assert-count 1 t:IBUFG
+select -assert-count 3 t:IBUF
 select -assert-count 1 t:OBUF
-select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
 

architecture/synth_xilinx/synth_xilinx_ise.ys

@@ -9,10 +9,9 @@ cd dff # Constrain all select calls below inside the top module
 stat
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
-select -assert-count 1 t:IBUF
-select -assert-count 1 t:IBUFG
+select -assert-count 2 t:IBUF
 select -assert-count 1 t:OBUF
-select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
 
 design -load read
 hierarchy -top dffe
@@ -23,8 +22,7 @@ cd dffe # Constrain all select calls below inside the top module
 stat
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
-select -assert-count 2 t:IBUF
-select -assert-count 1 t:IBUFG
+select -assert-count 3 t:IBUF
 select -assert-count 1 t:OBUF
-select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
 

architecture/synth_xilinx/synth_xilinx_noiopad.ys

@@ -9,10 +9,9 @@ cd dff # Constrain all select calls below inside the top module
 stat
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
-select -assert-count 1 t:IBUF
-select -assert-count 1 t:IBUFG
+select -assert-count 2 t:IBUF
 select -assert-count 1 t:OBUF
-select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
 
 design -load read
 hierarchy -top dff

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_read_wider.ys

@@ -16,7 +16,11 @@ cd asym_ram_sdp_read_wider
 stat
 #Vivado synthesizes 1 RAMB18E1.
 select -assert-count 2 t:BUFG
-select -assert-count 1 t:LUT2
-select -assert-count 4 t:RAMB18E1
+select -assert-count 271 t:FDRE
+select -assert-count 23 t:LUT2
+select -assert-count 262 t:LUT6
+select -assert-count 115 t:MUXF7
+select -assert-count 49 t:MUXF8
+select -assert-count 128 t:RAM64M
 
-select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT6 115 t:MUXF7 49 t:MUXF8 128 t:RAM64M %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_write_wider.ys

@@ -16,9 +16,7 @@ cd asym_ram_sdp_write_wider
 stat
 #Vivado synthesizes 1 RAMB18E1.
 select -assert-count 2 t:BUFG
-select -assert-count 9 t:FDRE
-select -assert-count 1 t:INV
-select -assert-count 6 t:LUT3
-select -assert-count 8 t:RAM128X1D
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:RAMB18E1
 
-select -assert-none t:BUFG t:FDRE t:INV t:LUT3 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys

@@ -18,12 +18,11 @@ stat
 select -assert-count 2 t:BUFG
 select -assert-count 200 t:FDRE
 select -assert-count 15 t:LUT2
-select -assert-count 64 t:LUT3
+select -assert-count 68 t:LUT3
 select -assert-count 4 t:LUT4
-select -assert-count 91 t:LUT5
-select -assert-count 719 t:LUT6
+select -assert-count 88 t:LUT5
+select -assert-count 716 t:LUT6
 select -assert-count 328 t:MUXF7
 select -assert-count 148 t:MUXF8
 
-
 select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_fsm_1.ys

@@ -11,11 +11,10 @@ cd fsm_1 # Constrain all select calls below inside the top module
 #Vivado synthesizes 2 LUT5, 2 LUT4, 1 LUT3, 4 FDRE.
 stat
 select -assert-count 1 t:BUFG
-select -assert-count 6 t:FDRE
+select -assert-count 5 t:FDRE
+select -assert-count 1 t:FDSE
 select -assert-count 2 t:LUT2
 select -assert-count 3 t:LUT3
-select -assert-count 4 t:LUT6
-select -assert-count 2 t:MUXF7
-select -assert-count 1 t:MUXF8
+select -assert-count 2 t:LUT5
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_init_file.ys

@@ -16,7 +16,6 @@ cd rams_init_file
 stat
 #Vivado synthesizes 1 RAMB18E1.
 select -assert-count 1 t:BUFG
-select -assert-count 32 t:FDRE
-select -assert-count 32 t:RAM64X1D
+select -assert-count 1 t:RAMB18E1
 
-select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
+select -assert-none t:BUFG t:RAMB18E1 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys

@@ -20,8 +20,8 @@ select -assert-count 1 t:BUFG
 select -assert-count 16 t:FDRE
 select -assert-count 5 t:LUT2
 select -assert-count 4 t:LUT3
-select -assert-count 13 t:LUT4
-select -assert-count 23 t:LUT5
+select -assert-count 11 t:LUT4
+select -assert-count 25 t:LUT5
 select -assert-count 32 t:LUT6
 select -assert-count 128 t:RAM128X1D
 

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom.ys

@@ -16,7 +16,6 @@ cd rams_sp_rom
 stat
 #Vivado synthesizes 1 RAMB18E1.
 select -assert-count 1 t:BUFG
-select -assert-count 20 t:RAM64X1D
-select -assert-count 20 t:FDRE
+select -assert-count 1 t:RAMB18E1
 
-select -assert-none t:BUFG t:RAM64X1D t:FDRE %% t:* %D
+select -assert-none t:BUFG t:RAMB18E1 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys

@@ -18,9 +18,11 @@ stat
 
 select -assert-count 1 t:BUFG
 select -assert-count 16 t:FDRE
-select -assert-count 44 t:LUT5
+select -assert-count 1 t:LUT2
+select -assert-count 8 t:LUT3
+select -assert-count 36 t:LUT5
 select -assert-count 38 t:LUT6
 select -assert-count 10 t:MUXF7
 select -assert-count 128 t:RAM128X1D
 
-select -assert-none t:BUFG t:LUT2 t:FDRE t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_registers_1.ys

@@ -8,5 +8,4 @@ cd registers_1 # Constrain all select calls below inside the top module
 #Vivado synthesizes 1 BUFG, 8 FDRE.
 select -assert-count 1 t:BUFG
 select -assert-count 8 t:FDRE
-select -assert-count 9 t:LUT2
-select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
+select -assert-none t:BUFG t:FDRE %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys

@@ -18,7 +18,7 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:DSP48E1
 select -assert-count 32 t:FDRE
-select -assert-count 65 t:LUT2
+select -assert-count 32 t:LUT2
 select -assert-count 16 t:MUXCY
 select -assert-count 17 t:XORCY
 

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys

@@ -17,9 +17,9 @@ stat
 #Vivado synthesizes 1 RAMB36E1, 28 FDRE.
 select -assert-count 1 t:BUFG
 select -assert-count 53 t:FDRE
-select -assert-count 1 t:INV
-select -assert-count 9 t:LUT2
-select -assert-count 11 t:LUT3
+select -assert-count 2 t:LUT2
+select -assert-count 10 t:LUT3
+select -assert-count 1 t:LUT4
 select -assert-count 16 t:RAM128X1D
 
-select -assert-none t:BUFG t:FDRE t:INV t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:RAM128X1D %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys

@@ -17,8 +17,8 @@ cd xilinx_ultraram_single_port_read_first
 select -assert-count 1 t:BUFG
 select -assert-count 53 t:FDRE
 select -assert-count 1 t:INV
-select -assert-count 8 t:LUT2
-select -assert-count 11 t:LUT3
+select -assert-count 1 t:LUT2
+select -assert-count 10 t:LUT3
 select -assert-count 16 t:RAM128X1D
 
 select -assert-none t:BUFG t:FDRE t:INV t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_write_first.ys

@@ -16,9 +16,9 @@ cd xilinx_ultraram_single_port_write_first
 #Vivado synthesizes 1 RAMB18E1, 28 FDRE.
 select -assert-count 1 t:BUFG
 select -assert-count 44 t:FDRE
+select -assert-count 1 t:LUT2
+select -assert-count 2 t:LUT3
 select -assert-count 8 t:LUT5
-select -assert-count 8 t:LUT2
-select -assert-count 3 t:LUT3
 select -assert-count 16 t:RAM128X1D
 
-select -assert-none t:BUFG t:FDRE t:LUT5 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT5 t:RAM128X1D %% t:* %D