Unverified Commit 8761f0f1 by Miodrag Milanović Committed by GitHub

Merge pull request #90 from YosysHQ/eddie/verific_enum

tests: verific/typerange; YosysHQ/yosys#1999
parents 69ee7e02 00e5faef
SUBDIRS = opers sva vhdl SUBDIRS = opers sva vhdl typerange
all: $(addsuffix /.stamp,$(SUBDIRS)) all: $(addsuffix /.stamp,$(SUBDIRS))
touch .stamp touch .stamp
......
run-test.mk
/*.log
/*.status
/.stamp
all:
bash run-test.sh
touch .stamp
clean:
rm -f *.status
rm -f .stamp
rm -f .start
.PHONY: all
typedef enum logic [1:0] {
ts0, ts1, ts2, ts3
} states_t;
module top(input clk, input states_t din, output states_t dout);
states_t r;
always @(posedge clk) begin
r <= din;
dout <= r;
end
endmodule
package pack is
type states_t is (ts0, ts1, ts2, ts3);
end package;
library ieee;
use ieee.std_logic_1164.all;
use work.pack.all;
entity top is
port (clk : in std_logic; din : in states_t; dout : out states_t);
end entity;
architecture arch of top is
signal r : states_t;
begin
process (clk)
begin
if rising_edge(clk) then
r <= din;
dout <= r;
end if;
end process;
end arch;
verific -sv enum.sv
hierarchy -top top
select -assert-count 3 a:wiretype=\\states_t
select -assert-count 3 a:enum_value_00=\\ts0
select -assert-count 3 a:enum_value_01=\\ts1
select -assert-count 3 a:enum_value_10=\\ts2
select -assert-count 3 a:enum_value_11=\\ts3
design -reset
read_verilog -sv <<EOT
typedef enum logic [1:0] {
ts0, ts1, ts2, ts3
} states_t;
module top(input clk, input [1:0] din, output [1:0] dout);
states_t foo = din, bar; // Note: not quite legal SV, but necessary
// to workaround Yosys not supporting
// enums in ports
states_t r;
always @(posedge clk) begin
r <= foo;
bar <= r;
end
assign dout = bar;
endmodule
EOT
hierarchy -top top
select -assert-count 3 a:wiretype=\\states_t
select -assert-count 3 a:enum_value_00=\\ts0
select -assert-count 3 a:enum_value_01=\\ts1
select -assert-count 3 a:enum_value_10=\\ts2
select -assert-count 3 a:enum_value_11=\\ts3
design -reset
verific -vhdl enum.vhd
hierarchy -top top
select -assert-count 3 a:wiretype=\\states_t
select -assert-count 3 a:enum_value_00=\\ts0
select -assert-count 3 a:enum_value_01=\\ts1
select -assert-count 3 a:enum_value_10=\\ts2
select -assert-count 3 a:enum_value_11=\\ts3
module top ;
enum {A, B} x;
endmodule
verific -sv enum_anon.sv
hierarchy -top top
select -assert-count 0 a:wiretype
select -assert-count 0 a:enum_value*
select -assert-count 0 a:enum_type
design -reset
read_verilog -sv enum_anon.sv
hierarchy -top top
select -assert-count 0 a:wiretype
select -assert-count 0 a:enum_value*
select -assert-count 1 a:enum_type
#!/usr/bin/env bash
set -e
{
echo "all::"
for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @touch .start"
echo " @echo 'Running $x..'"
echo " @(yosys -ql ${x%.ys}.log $x && echo PASS > ${x%.ys}.status) || echo FAIL > ${x%.ys}.status"
done
for s in *.sh; do
if [ "$s" != "run-test.sh" ]; then
echo "all:: run-$s"
echo "run-$s:"
echo " @touch .start"
echo " @echo 'Running $s..'"
echo " @(bash $s &> ${s%.sh}.log && echo PASS > ${s%.sh}.status) || echo FAIL > ${s%.sh}.status"
fi
done
} > run-test.mk
exec ${MAKE:-make} -f run-test.mk
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