Commit 00e5faef by Eddie Hung

Add anonymous testcase

parent 778e246a
module top ;
enum {A, B} x;
endmodule
verific -sv enum_anon.sv
hierarchy -top top
select -assert-count 0 a:wiretype
select -assert-count 0 a:enum_value*
select -assert-count 0 a:enum_type
design -reset
read_verilog -sv enum_anon.sv
hierarchy -top top
select -assert-count 0 a:wiretype
select -assert-count 0 a:enum_value*
select -assert-count 1 a:enum_type
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